ADV7184BSTZ Analog Devices Inc, ADV7184BSTZ Datasheet - Page 45

• Manufacturer Part Number: ADV7184BSTZ
• Description: IC DECODER VID SDTV MULTI 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7184BSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 10bit
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 550mW
• No. Of Input Channels: 12
• Supply Voltage Range: 1.65V To 2V, 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Tv /: RoHS Compliant
• Input Format: Analogue
• Output Format: Digital
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RANGE, Range Selection, Address 0x04 [0]
AV codes (as per ITU-R BT.656, formerly known as CCIR 656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and therefore are not to be used
for active video. Additionally, the ITU specifies that the nominal
range for video should be restricted to values between 16 and
235 for luma and between 16 and 240 for chroma.
The RANGE bit allows the user to limit the range of values
output by the ADV7184 to the recommended value range. This
ensures that the reserved values of 255d (0xFF) and 00d (0x00)
are not presented on the output pins unless they are part of an
AV code header.
Table 58. RANGE Function
RANGE
0
1 (default)
AUTO_PDC_EN, Automatic Programmed Delay Control,
Address 0x27 [6]
Enabling AUTO_PDC_EN activates a function within the
ADV7184 that automatically programs LTA [1:0] and CTA [2:0]
to have the chroma and luma data match delays for all modes of
operation.
0—The ADV7184 uses the LTA [1:0] and CTA [2:0] values for
delaying luma and chroma samples. Refer to the LTA [1:0],
Luma Timing Adjust, Address 0x27 [1:0] and the CTA [2:0],
Chroma Timing Adjust, Address 0x27 [5:3] sections.
1 (default)—The ADV7184 automatically programs the LTA
and CTA values to have luma and chroma aligned at the output.
Manual registers LTA [1:0] and CTA [2:0] are not used.
LTA [1:0], Luma Timing Adjust, Address 0x27 [1:0]
These bits allow the user to specify a timing difference between
chroma and luma samples.
Note that there is a certain functionality overlap with the CTA [2:0]
bits. For manual programming, use the following defaults:
•
•
•
Table 59. LTA [1:0] Function
LTA [1:0]
00 (default)
01
10
11
CVBS input LTA [1:0] = 00
Y/C input LTA [1:0] = 01
YPrPb input LTA [1:0] = 01
16 ≤ Y ≤ 235
1 ≤ Y ≤ 254
Description
No delay
Luma 1 clock (37 ns) delayed
Luma 2 clock (74 ns) early
Luma 1 clock (37 ns) early
Description
16 ≤ C ≤ 240
1 ≤ C ≤ 254
Rev. A | Page 45 of 112
CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3]
These bits allow the user to specify a timing difference between
chroma and luma samples. This may be used to compensate for
external filter group delay differences in the luma vs. chroma path
and to allow a different number of pipeline delays while processing
the video downstream. Review this functionality together with
that of the LTA [1:0] bits.
The chroma can be delayed or advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, when no delay
by luma pixel steps are allowed.
For manual programming, use the following defaults:
•
•
•
Table 60. CTA Function
CTA [2:0]
000
001
010
011 (default)
100
101
110
111
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
The HS begin (HSB) and HS end (HSE) bits allow the user to
position the HS output pin anywhere within the video line.
The values in HSB [10:0] and HSE [10:0] are measured in pixel
units from the falling edge of HS. Using both values, the user
can program both the position and length of the HS output signal.
HSB [10:0], HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The position of this edge is controlled by placing a binary
number into HSB [10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 26). HSB [10:0] is set
to 00000000010, which is two LLC1 clock cycles from Count [0].
The default value of HSB [10:0] is 0x002, indicating that the HS
pulse starts two pixels after the falling edge of HS.
CVBS input CTA [2:0] = 011
Y/C input CTA [2:0] = 101
YPrPb input CTA [2:0] = 110
HSB [10:0]: sets beginning of HS signal
HSE [10:0]: sets end of HS signal
PHS: sets polarity of HS
Description
Not used
Chroma plus two chroma pixels (early)
Chroma plus one chroma pixel (early)
No delay
Chroma minus one chroma pixel (delayed)
Chroma minus two chroma pixels (delayed)
Chroma minus three chroma pixels (delayed)
Not used
ADV7184