AD1892JR Analog Devices Inc, AD1892JR Datasheet
AD1892JR
Specifications of AD1892JR
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AD1892JR Summary of contents
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FEATURES Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU, S/PDIF Compatible Digital Audio Receiver and Asynchronous Sample Rate Converter Status Pins and Microprocessor Interfaces for Stand-Alone and Microcontroller-Oriented Operation Integrated Channel Status Buffer and Q-Channel Subcode Buffer (Supports EIAJ CP-2401) ® ...
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AD1892–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltage Ambient Temperature Output Sample Frequency (F ) SOUT MCLK Input Word Width Load Capacitance All minimums and maximums tested except as noted. 1 PERFORMANCE Dynamic Range ( kHz, –60 ...
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... Specifications subject to change without notice. Model AD1892JR AD1892JRRL – +85 C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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AD1892 (continued from Page 1) PRODUCT OVERVIEW (Continued) In addition to the Q-channel subcode and Channel Status buff- ers, the AD1892 includes two 8-bit control registers and two 8- bit status registers. The output data interface may be configured 2 ...
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Decoded Channel Status Outputs (Continued) Pin Name SOIC I/O Description consumer mode the inverse Channel Status Bit 3, Byte 0 (C3, pre-emphasis indicates that the audio material has been pre-emphasized; CC ...
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AD1892 Subframe Status Outputs Pin Name SOIC I/O Description NOSIG 12 O NOSIG (No Signal) is asserted HI when no biphase-mark input is applied to the AD1892 when either the input sample rate is too high for the applied master ...
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Power Supply Connections Pin Name SOIC I/O Description DV 22 Digital Supply nominal supply voltage. DD DGND 7 Digital Ground nominal supply connection. Miscellaneous Pin Name SOIC I/O Description MCLK 28 I Master clock. Must be ...
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AD1892 SERIAL DIGITAL AUDIO TRANSMISSION STANDARDS The AD1892 can receive S/PDIF (Sony/Philips Digital Interface Format), AES/EBU (Audio Engineering Society/European Broadcasting Union, also known as AES3-1992), IEC-958 (International Electrotechnical Commission) and CP-340 (EIAJ [Electronic Industry Association of Japan] CP-1201) serial streams. ...
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FRAME PREAMBLE AUX DATA Figure 5. Block, Frame and Subframe Organization As noted above, the Channel Status ...
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AD1892 BYTE 0 BIT 0 PRO = 0 (CONSUMER) 0 CONSUMER USE OF CHANNEL STATUS BLOCK. 1 PROFESSIONAL USE OF CHANNEL STATUS BLOCK. AUDIO BIT 1 0 DIGITAL AUDIO. 1 NON-AUDIO. CAN BE USED TO INDICATE AC-3 DATA. COPY/COPYRIGHT. BIT ...
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BYTE 2 BITS SOURCE NUMBER UNSPECIFIED ...
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AD1892 BYTE 2 BITS AUX: USE OF AUXILIARY SAMPLE BITS NOT DEFINED. MAXIMUM AUDIO WORD LENGTH IS 20 BITS USED FOR MAIN AUDIO. MAXIMUM AUDIO WORD LENGTH IS 24 BITS. 0 ...
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SERIAL CONTROL PORT The serial control port on the AD1892 is a bidirectional inter- face that allows external microcontrollers and microprocessors to gain access to the two on-chip byte-wide control registers and to the sixteen on-chip byte-wide status registers. The ...
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AD1892 CONTROL/STATUS REGISTER ARCHITECTURE The AD1892 includes two byte-wide control registers, two byte-wide status registers, four Channel Status registers and ten ADDRESS 0000 RESERVED RESERVED STEREO/ 00 0001 MUTE MONO ADDRESS 0000 RESERVED RESERVED ...
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ADDRESS PHASE CH. STATUS INTERRUPT 00 0000 LOCK CRC ERROR (MIRRORS PIN) 00 0001 NOT DEFINED NOT DEFINED NOT DEFINED SAMPLE SAMPLE LOCKED/ 00 0010 FREQUENCY FREQUENCY UNLOCKED USER BIT USER BIT USER BIT 00 0011 MANAGEMENT ...
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AD1892 The AD1892 includes an on-chip 10 byte Q-channel subcode buffer that is defined in consumer mode only. MiniDisc and Compact Disc systems use the Q-channel subcode information to convey format, track, index and timing information. The Q- channel is ...
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The incoming 16-bit CRC Word (Q82 through Q97) is routed to the AD1892 CRC circuit block. The CRC block generates a 16-bit polynomial against the first 80 bits of the incoming Q-channel subcode and flags a CRC error if the ...
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AD1892 LRCLK LEFT CHANNEL OUTPUT BCLK OUTPUT SDATA LSB MSB MSB–1 MSB–2 OUTPUT Note that in 16-bit output mode, the AD1892 is capable BCLK frequency “packed mode” where the MSB is SOUT left-justified to an LRCLK ...
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AD1892 28 MCLK 23 SYNC AD1892 28 MCLK 23 SYNC AD1892 28 MCLK 23 SYNC Figure 32. Multiple AD1892 Synchronization Using SYNC CHANNEL STATUS REGISTER D TYPE REGISTER LEDS CONTROLLER, ...
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AD1892 0.01 F CONSUMER S/PDIF INPUT 75 75 CONN 0.01 F RCA PHONE CONNECTOR AES/EBU INPUT 38R3 3V–10V p 38R3 3 2 110 BAT54S OR BAS70-04 +5V 0. DGND ...
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Dither The AD1892 can be programmed to add triangular Probability Distribution Function (PDF) dither to the digital audio samples advisable to add dither when the input word width exceeds the output word width, e.g., the input word is ...
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AD1892 TIMING DIAGRAMS MCLK PD/RST MCLK INPUT (NOT TO SCALE) BCLK OUTPUT t LRCLK OUTPUT t SDATA OUTPUT LEFT-JUSTIFIED MODE t DDP SDATA OUTPUT 2 1 S-JUSTIFIED MODE SDATA OUTPUT RIGHT-JUSTIFIED MODE CS CCLK SDI SDO t MCP t PDRP ...
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CSPW CSCLK CON/PRO Figure 38. Channel Status and Clock Timing MCLK INPUT SYNC INPUT BCLK OUTPUT LRCLK OUTPUT SDATA OUTPUT NOTE: THIS DIAGRAM SHOWS SECOND AND SUBSEQUENT SYNC INPUT SYNCHRONIZED OUTPUT CLOCK AND DATA ...
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AD1892 Typical Performance Plots –0.90 –0.92 –0.94 –0.96 –0.98 –1.00 –1.02 –1.04 –1.06 –1.08 –1.10 100 1k Hz Figure 42. Frequency Response, –1 dB Full-Scale Input –80 –84 –88 –92 –96 –100 –104 –108 –112 –116 –120 100 1k Hz ...