ADV7185KST Analog Devices Inc, ADV7185KST Datasheet - Page 20

• Manufacturer Part Number: ADV7185KST
• Description: IC VIDEO DECODER NTSC 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Decoderr

Specifications of ADV7185KST

• Rohs Status: RoHS non-compliant
• Applications: DVD-RAM, Projectors, TV
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

ADV7185
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7185 except the subaddress register, which is a write only
register. The subaddress register determines which register the
next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. Then a read/write operation is performed from/to the
target address, which then increments to the next address until a
stop command on the bus is performed.
Register Name
BASIC BLOCK
Input Control
Video Selection
Video Enhancement Control
Output Control
Extended Output Control
General-Purpose Output
Reserved
FIFO Control
Contrast Control
Saturation Control
Brightness Control
Hue Control
Default Value Y
Default Value C
Temporal Decimation
Power Management
Status Register
Info Register
Addr (Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Table II. Subaddress Register
–20–
REGISTER PROGRAMMING
The following section describes each register in terms of its
configuration.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write only register. After the
part has been accessed over the bus and a read/write operation is
selected, the subaddress is set up. The subaddress register deter-
mines to/from which register the operation takes place.
Table II shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
Register Name
ADVANCED BLOCK
Reserved
Analog Control (Internal)
Analog Clamp Control
Digital Clamp Control 1
Digital Clamp Control 2
Shaping Filter Control
Reserved
Comb Filter Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Color Subcarrier Control 1
Color Subcarrier Control 2
Color Subcarrier Control 3
Color Subcarrier Control 4
Pixel Delay Control
Manual Clock Control 1
Manual Clock Control 2
Manual Clock Control 3
Auto Clock Control
AGC Mode Control
Chroma Gain Control 1
Chroma Gain Control 2
Luma Gain Control 1
Luma Gain Control 2
Manual Gain Shadow Control 1
Manual Gain Shadow Control 2
Misc Gain Control
HSync Position Control 1
HSync Position Control 2
HSync Position Control 3
Polarity Control
Reserved
Reserved
Reserved
Reserved
Addr (Hex)
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
44
45
F1
F2
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