ADV7185KST Analog Devices Inc, ADV7185KST Datasheet
ADV7185KST
Specifications of ADV7185KST
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ADV7185KST Summary of contents
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FEATURES Analog Video to Digital YCrCb Video Decoder: NTSC-(M/N), PAL-(B/D/G/H/I/M/N) ® ADV 7185 Integrates Two 12-Bit ADCs Clocked from a Single 27 MHz Crystal Dual Video Clocking Schemes: Line-Locked Clock Compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™) 3-Line ...
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ADV7185–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (each ADC) Accuracy (each ADC) 3 Integral Nonlinearity 3 Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS ...
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VIDEO PERFORMANCE SPECIFICATIONS Parameter 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity 2 NOISE SPECIFICATIONS SNR (Ramp) Analog Front End Channel Crosstalk LOCK TIME AND JITTER 2 SPECIFICATIONS Horizontal Lock Time Horizontal Recovery Time Horizontal Lock Range Line Length ...
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ADV7185 1 TIMING SPECIFICATIONS Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency PORT SCL Clock Frequency SCL Min Pulsewidth High SCL Min Pulsewidth Low Hold Time (Start Condition Setup Time (Start ...
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SDATA SCLOCK OUTPUTS P0–P19, HREF, VREF, VSYNC, HSYNC, FIELD, DV Figure 2. LLC Clock, Pixel Port, and Control Outputs Timing Diagram Figure 3. Pixel Port and Control Outputs in CAPI and SCAPI Mode Timing Diagram REV ...
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... ADV7185 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. VS/ACTIVE HS/ACTIVE DVSSIO DVDDIO DVSS2 DVDD2 AFF HFF/QCLK/GL AEF DVSSIO DVDDIO CLKIN Model ADV7185KST + 0 PIN CONFIGURATION PIN 1 2 IDENTIFIER 3 4 P15 5 ...
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Pin Mnemonic 1 VS/VACTIVE 2 HS/HACTIVE 3, 14 DVSSIO 4, 15 DVDDIO 5–8, 17–24, P19–P0 32–35, 73–76 9, 31, 71 DVSS1–DVSS3 10, 30, 72 DVDD1–DVDD3 11 AFF 12 HFF/QCLK/GL 13 AEF 16 CLKIN 25 LLCREF 26 LLC2 27 LLC1/PCLK 28 ...
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ADV7185 Pin Mnemonic 39, 40, 47, 53, AVSS 56, 63 41, 43, 45, 57, AVSS1–AVSS6 59, 61 42, 44, 46, 58, AIN1–AIN6 60, 62 48, 49 CAPY1–CAPY2 50 AVDD 51 REFOUT 52 CML 54, 55 CAPC1–CAPC2 RESET 64 65 ISO ...
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Simplified Digital Interface On-Board Digital FIFO Optimized Programmable Video Source Modes: Broadcast TV VCR/Camcorder Security/Surveillance Integrated On-Chip Video Timing Generator Synchronous or Asynchronous Output Timing Line-Locked Clock Output Closed Captioning Passthrough Operation Vertical Blanking Interval ...
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ADV7185 clamping. Also, in YCrCb component input mode there are two clamp controllers used to control the luminance clamping and the CrCb clamping separately; there are, however, individual current clamps on the Cr and Cb inputs. User programmability is built ...
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LUMINANCE PROCESSING Figure 7 shows the luminance data path. The 12-bit data from the Y ADC is applied to an antialiasing low-pass filter that is designed to band-limit the input video signal such that aliasing does not occur. This filter ...
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ADV7185 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 0.5 1.0 1.5 2.0 FREQUENCY – MHz Figure 11. Luminance NTSC Narrow/Wide Notch Shaping Filter (Close-Up) 0 PAL NN1 PAL NN2 –10 PAL NN3 PAL W1 PAL ...
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CHROMINANCE PROCESSING Figure 17 shows the chrominance data path. The 12-bit data from the Y ADC (CVBS mode) or the C ADC (S-video) is first demodulated. The demodulation is achieved by multiplying by the locally generated quadrature subcarrier, where the ...
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ADV7185 OUTPUT INTERFACE Mode Selection Overview The ADV7185 supports three output interfaces: LLC-compatible synchronous pixel interface, the CAPI interface, and SCAPI interface. When the part is configured in the synchronous pixel interface mode, pixel and control data are output synchronous ...
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CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT REV. 0 Figure 21. NTSC End Even Field ...
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ADV7185 CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT Figure 23. PAL End Even Field (LLC ...
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Control and Pixel Interface FIFO Modes When the ADV7185 is configured to operate in this mode, pixel data generated within the part is buffered by a 512-pixel deep FIFO. Only active video pixels and control codes are written into the ...
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ADV7185 Manual Clock Control The ADV7185 offers several output clock mode options: the output clock frequency can be set by the input video line length, a fixed 27 MHz output user-programmable value. Informa- tion on the clock ...
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WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER SDATA SCLOCK REV. 0 SUB ADDR A(S) ...
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ADV7185 REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7185 except the subaddress register, which is a write only register. The subaddress register determines which register the next read or write operation ...
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Addr Register (Hex) D7 Input Control 00 VID SEL.3 VID SEL.2 VID SEL.1 VID SEL.0 INSEL.3 Video Selection 01 ASE Video Enhancement 02 Control Output Control 03 VBI EN Extended Output 04 BT656-4 Control General-Purpose 05 HL_EN Output Reserved 06 ...
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ADV7185 Addr Register (Hex) D7 Color Subcarrier 24 CSMF.23 Control 2 Color Subcarrier 25 CSMF.15 Control 3 Color Subcarrier 26 CSMF.7 Control 4 Pixel Delay Control 27 SWPC Manual Clock 28 FIX27E Control 1 Manual Clock 29 CLKVAL. CLKVAL. CLKVAL. ...
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Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 INSEL[3: VID_SEL[3: ...
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ADV7185 Table VII. Video Enhancement Control Register (Subaddress 02) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 YPM[2:0] 4 COR[1:0] RESERVED NOTES 1 Y ...
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Table IX. Extended Output Control Register (Subaddress 04) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 RANGE RESERVED DDOS[2: BT656-4 1 NOTES ...
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ADV7185 Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting SAT[7:0 *Saturation Adjust. Allows the user to adjust the saturation ...
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Table XVIII. Temporal Decimation Register (Subaddress 0E) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 TDE 2 TDC[1: TDR[3: ...
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ADV7185 Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 2 STATUS[7: NOTES 1 Read only 2 Provides information about the internal status ...
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Table XXIV. Digital Clamp Control 1 Register (Subaddress 15) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 DCCO[11:8] 2 DCFE DCT[1: ...
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ADV7185 Table XXVII. Comb Filter Control Register (Subaddress 19) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED CCM[1:0] 2 CCMB_AD NOTES 1 Chroma ...
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Table XXXII. Pixel Delay Control Register (Subaddress 27) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 1 0 CTA[2: RESERVED ...
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ADV7185 Table XXXVI. Auto Clock Control Register (Subaddress 2B) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED ACLKN[2:0 ...
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Table XL. Luma Gain Control 1 Register (Subaddress 2F) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 LMG[11:8] RESERVED LAGT[1: ...
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ADV7185 Table XLV. HSync Position Control 1 Register (Subaddress 34) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 1 0 HSE[9: HSB[9:8] NOTES 1 ...
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Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 PCLK 2 PFF 3 PDV PLLCR 6 0 PVS PHVR ...
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ADV7185 Table XLIX. Resample Control Register (Subaddress 44) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 0 FSC_INV RESERVED 0 *Color Subcarrier RTCO Inversion. ...
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Table LIII. Power-On Reset Values for MPU Registers Addr Register (Hex) BASIC BLOCK Input Control 00 Video Selection 01 Video Enhancement Control 02 Output Control 03 Extended Output Control 04 General-Purpose Output 05 Reserved 06 FIFO Control 07 Contrast Control ...
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ADV7185 Appendix BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7185 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the ...
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AVDD 33 F AVSS AVSS DVSS DVDD 33 F DVSS AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AVSS AVSS AVSS AVSS INPUT SWITCH OVER 0.1 F 0.1 F AVSS AVSS 0.1 F 0.1 F AVSS AVSS 0.1 F DVDD DVSS DVDD ...
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ADV7185 COPLANARITY CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 80-Lead Thin Plastic Quad Flatpack [LQFP] ...