adv7181b Analog Devices, Inc., adv7181b Datasheet
adv7181b
Available stocks
Related parts for adv7181b
adv7181b Summary of contents
Page 1
... The output control signals allow glueless interface connections in almost any application. The ADV7181B modes are set up over a 2-wire, serial, bidirectional port (I The ADV7181B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7181B is available in two packages, a small 64-lead LQFP Pb-free package and a 64-lead LFCSP package ...
Page 2
... ADV7181B TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ 9 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Analog Front End ........................................................................... 13 Analog Input Muxing ................................................................ 13 Global Control Registers ...
Page 3
... Changes to Table 54 ........................................................................41 Changes to Table 55 ........................................................................42 Changes to Table 83 ........................................................................67 Changes to Table 84 ........................................................................71 Changes to Table 85 ........................................................................88 Changes to Table 86 ........................................................................89 Changes to Table 87 ........................................................................90 Changes to Table 88 ........................................................................91 Added XTAL Load Capacitor Value Selection Section..............96 Replaced Figure 45..........................................................................98 7/04—Revision 0: Initial Version Rev Page 3 of 100 ADV7181B ...
Page 4
... The ADV7181B can process a variety of VBI data services such as close captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1×/2×, and extended data service (XDS). The ADV7181B is fully Macrovision certified ...
Page 5
... FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev Page 5 of 100 ADV7181B ...
Page 6
... ADV7181B SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD VDD otherwise noted. Table Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage ...
Page 7
... VDD VDDIO Symbol Test Conditions DP CVBS I/P, modulate 5-step DG CVBS I/P, modulate 5-step LNL CVBS I/P, 5-step Luma ramp Luma flat field HUE CL_AC CVBS I/P CVBS I/P Rev Page 7 of 100 ADV7181B = 2.0 V; VDD Min Typ Max Unit 0.6 0.7 Degrees 0.6 0.7 % 0.6 0 ...
Page 8
... ADV7181B TIMING SPECIFICATIONS Guaranteed by characterization 3. 3. VDD operating temperature range, unless otherwise noted. Table Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability PORT SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) ...
Page 9
... PCB with solid ground plane, 64-lead LQFP Figure Timing SFL Figure 3. Pixel Port and Control Output Timing Rev Page 9 of 100 ADV7181B Min Typ Max 45.5 9 Unit °C/W °C/W °C/W °C/W ...
Page 10
... ADV7181B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO –0 +0.3 V VDDIO VDD –0 +0.3 V VDD VDD D – P –0 VDDIO VDD D – ...
Page 11
... ADV7181B 8 TOP VIEW 9 (Not to Scale Figure 4. 64-Lead LFCSP/LQFP Pin Configuration Rev Page 11 of 100 AIN5 48 AIN4 47 AIN3 46 AGND 45 CAPC2 44 AGND 43 CML 42 REFOUT 41 AVDD 40 CAPY2 39 CAPY1 38 AGND 37 AIN2 36 AIN1 35 DGND ADV7181B ...
Page 12
... MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 28.6363 MHz crystal or left connect if an external 3 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the crystal must be a fundamental crystal. ...
Page 13
... Figure 5 outlines the overall structure of the input muxing provided in the ADV7181B. A maximum of six CVBS inputs can be connected and decoded by the ADV7181B. As seen in the Pin Configuration and Function Description section, these analog input pins lie near each other; therefore, a careful design of the PCB layout is required, such as ground shielding between all signals routed through tracks that are physically close together ...
Page 14
... AIN3 1101 AIN5 1110 No connection 1111 No connection CONNECTING ANALOG SIGNALS TO ADV7181B SET INSEL[3:0] TO CONFIGURE ADV7181B TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 CONFIGURE ADC INPUTS USING MUXING CONTROL BITS (ADC_sw_man_en, ADC0_sw, ADC1_sw, ADC2_sw) Figure 6. Input Muxing Overview ADC1_sw[3:0] ADC1 Connected to ...
Page 15
... Register control bits listed in this section affect the whole chip. POWER-SAVE MODES Power-Down The digital core of the ADV7181B can be shut down by using a pin ( PWRDN ) and a bit (PWRDN); see below. The PDBP controls which of the two has the higher priority. By default, the pin ( PWRDN ) is given priority ...
Page 16
... Three-State LLC Driver TRI_LLC, Address 0x1D[7] This bit allows the output drivers for the LLC pin of the ADV7181B to be three-stated. For more information on three- state control, see the Three-State Output Drivers and the Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_XX bits ...
Page 17
... SFL pin. Polarity LLC Pin PCLK Address 0x37[0] The polarity of the clock that leaves the ADV7181B via the LLC pin can be inverted using the PCLK bit. Changing the polarity of the LLC clock output can be necessary to meet the setup-and-hold time expectations of follow-on chips ...
Page 18
... IDENTIFICATION IDENT[7:0] Address 0x11[7:0] The register identification of the revision of the ADV7181B. An identification value of 0x11 indicates the ADV7181 released silicon. An identification value of 0x13 indicates the ADV7181B silicon. STATUS 1 STATUS_1[7:0] Address 0x10[7:0] This read-only register provides information about the internal status of the ADV7181B. ...
Page 19
... RECOVERY A block diagram of the ADV7181B’s standard definition processor (SDP) is shown in Figure 7. The ADV7181B can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a luminance and chrominance path. If the input video composite type (CVBS), both processing paths are fed with the CVBS input. ...
Page 20
... The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure that the ADV7181B outputs 720 active pixels per line. The sync processing on the ADV7181B also includes the ...
Page 21
... SELECT THE RAW LOCK SIGNAL SRLS FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2: COUNTER INTO LOCK COUNTER OUT OF LOCK 1 FSCLE Figure 8. Lock-Related Signal Path Rev Page 21 of 100 ADV7181B STATUS 1 [0] STATUS 1 [1] MEMORY ...
Page 22
... Bits[1:0] in Status Register 1. This bit must be set to 0 when operating the ADV7181B in YPrPb component mode to generate a reliable HLOCK status bit. When FSCLE is set to 0 (default), the overall lock status is only dependent on horizontal sync lock ...
Page 23
... ADV7181B cannot lock to the input video (automatic mode). • DEF_VAL_EN bit is set to high (forced output). The data that is finally output from the ADV7181B for the chroma side is Cr[7:0] = {DEF_C[7:4 0}, Cb[7:0] = {DEF_C[3:0 0}. DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb. ...
Page 24
... DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C[1] This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7181B cannot lock to the video signal. Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If the decoder is unlocked, it outputs noise. Setting DEF_VAL_EN to 1 (default) enables free-run mode, and a colored screen set by user-programmable Y, Cr and Cb values is displayed when the decoder loses lock ...
Page 25
... MHz. (In the case of 4× oversampled video, the ADCs sample at 54 MHz, and the first decima- tion is performed inside the DPP filters. Therefore, the data rate into the ADV7181B is always 27 MHz.) The ITU- R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video ...
Page 26
... An automatic mode is provided. Here, the ADV7181B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard ...
Page 27
... Rev Page 27 of 100 ADV7181B NO USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO Description Do not use Do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 ...
Page 28
... Y/C, or U/V interleaved for YPrPb input formats. • Chroma Antialias Filter (CAA). The ADV7181B over- samples the CVBS by a factor of 2 and the Chroma/PrPb by a factor decimating filter (CAA) is used to preserve the active video band and to remove any out-of- band components. The CAA filter has a fixed response. • ...
Page 29
... VOLTAGE MINIMUM VOLTAGE GAIN OPERATION The gain control within the ADV7181B is done on a purely digital basis. The input ADCs support a 9-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. Advantages of this architecture over the commonly used ...
Page 30
... ADV7181B Table 32. AGC Modes Input Video Type Luma Gain Any Manual gain luma CVBS Dependent on horizontal sync depth Peak white Y/C Dependent on horizontal sync depth Peak white YPrPb Dependent on horizontal sync depth Luma Gain LAGC[2:0] Luma Automatic Gain Control, Address 0x2C[7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path ...
Page 31
... Enable manual fixed gain mode: Set LAGC[2:0] to 000 BETCAM Enable Betacam Levels, Address 0x01[5] If YPrPb data is routed through the ADV7181B, the automatic gain control modes can target different video input levels, as outlined in Table 39. The BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit basically sets the target value for AGC operation ...
Page 32
... PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7181B may not work satisfactorily for poor input video signals. Table 41. CKILLTHR Function CKILLTHR[2:0] ...
Page 33
... The default value for DNR_TH[7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise. COMB FILTERS The comb filters of the ADV7181B have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the ...
Page 34
... ADV7181B NSFSEL[1:0] Split Filter Selection NTSC, Address 0x19[3:2] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection gives better performance on diagonal lines, but leaves more dot crawl in the final output image. The opposite is true for selecting a wide bandwidth split filter ...
Page 35
... Fixed 3-line chroma comb for CTAPSP = 10 Fixed 4-line chroma comb for CTAPSP = 11 Configuration Adaptive 5 lines (3 taps) luma comb Use low-pass/notch filter; see the Y-Shaping Filter section Fixed 3 lines (2 taps) luma comb Fixed 5 lines (3 taps) luma comb Fixed 3 lines (2 taps) luma comb Rev Page 35 of 100 ADV7181B ...
Page 36
... All data for Line 1 to Line 21 is passed through and available at the output port. The ADV7181B does not blank the luma data, and auto- matically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored ...
Page 37
... The RANGE bit allows the user to limit the range of values output by the ADV7181B to the recommended value range. In any case, it ensures that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part code header ...
Page 38
... ADV7181B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS using PHS The HS begin and HS end registers allow the user to freely position the HS output (pin) within the video line ...
Page 39
... When VSEHE is 1 (default), the VS pin changes state at the start of a line (even field). PVS Polarity VS, Address 0x37[5] The polarity of the VS pin can be inverted using the PVS bit. When PVS is 0 (default active high. When PVS active low. Rev Page 39 of 100 ADV7181B ...
Page 40
... ADV7181B PF Polarity FIELD, Address 0x37[3] The polarity of the FIELD pin can be inverted using the PF bit. The FIELD pin can be inverted using the PF bit. 525 1 2 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 262 263 264 265 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 ...
Page 41
... Vsync begin position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified. Rev Page 41 of 100 Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 0x41 0x84 0x06 LINE VSBHE 1 0.5 LINE ADV7181B ...
Page 42
... ADV7181B NVENDDELO NTSC Vsync End Delay on Odd Field, Address 0xE6[7] When NVENDDELO is 0 (default), there is no delay. Setting NVENDDELO to 1 delays Vsync from going low on an odd field by a line relative to NVEND. NVENDDELE NTSC Vsync End Delay on Even Field, Address 0xE6[6] When NVENDDELE is set to 0 (default), there is no delay ...
Page 43
... For all NTSC/PAL field timing controls, both the F bit in the AV code and the Field signal on the FIELD pin are modified. Rev Page 43 of 100 0 NO NFTOGDELE 1 ADDITIONAL DELAY BY 1 LINE Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 0x41 0x84 0x06 ADV7181B ...
Page 44
... ADV7181B 622 623 624 625 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 Figure 25. PAL Default (BT.656). The Polarity and F is Embedded in the Data 622 623 624 625 OUTPUT VIDEO ...
Page 45
... PVENDSIGN PAL Vsync End Sign, Address 0xE9[5] Setting PVENDSIGN to 0 (default) delays the end of Vsync. Set for user manual programming. Setting PVENDSIGN to 1 advances the end of Vsync. Not recommended for user programming. Rev Page 45 of 100 ADV7181B 1 PVENDSIGN 0 ADVANCE END OF DELAY END OF VSYNC ...
Page 46
... FIELD TOGGLE Figure 29. PAL F Toggle SYNC PROCESSING The ADV7181B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If preferred, the blocks can be disabled via the following two I ENHSPLL Enable Hsync Processor, Address 0x01[6] ...
Page 47
... EDTV3[5] is reserved for future use and, for now, contains a 0. The three LSBs of the EDTV waveform are currently not supported. WSS1[7: START RUN-IN CODE 38.4μs 42.5μs Figure 30. WSS Data Extraction Rev Page 47 of 100 WSS2[5: ACTIVE VIDEO ADV7181B ...
Page 48
... ADV7181B Table 57. WSS Access Information Signal Name Register Location WSS1[7:0] WSS 1[7:0] WSS2[5:0] WSS 2[5:0] 0 Table 58. EDTV Access Information Signal Name Register Location EDTV1[7:0] EDTV 1[7:0] EDTV2[7:0] EDTV 2[7:0] EDTV3[7:0] EDTV 3[7:0] CGMS Data Registers CGMS1[7:0], Address 0x96[7:0] CGMS2[7:0], Address 0x97[7:0] CGMS3[7:0], Address 0x98[7:0] Figure 32 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers ...
Page 49
... Its end is programmable via LB_EL[3:0]. Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7181B finds at least two black lines followed by some more nonblack video, for example, the subtitle, and is then followed by the remainder of the bottom black block, it reports back a midcount via LB_LCM[7:0] ...
Page 50
... ITU-R BT.1364. • Checksum byte. Table 63 lists the values within a generic data packet that are output by the ADV7181B in 8-bit format. In 8-bit systems, Bits D1 and D0 in the data packets are disregarded. Rev Page 50 of 100 2 C, but is inserted ...
Page 51
... GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). Padding bytes are then added where necessary. Rev Page 51 of 100 ADV7181B OPTIONAL PADDING CHECK BYTES SUM D[2] ...
Page 52
... ADV7181B • CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet calculated by summing up D[8:2] of DID, SDID, the data count byte, and all UDWs, and ignoring any overflow during the summation. Since all data bytes that are used to calculate the checksum have their two LSBs set to 0, the CS[1:0] bits are also always 0 ...
Page 53
... User data-words UDW padding 0x200 UDW padding 0x200 CS[2] CS[1] CS[0] Checksum D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID 0 0 Data count User data-words 0 0 User data-words 0 0 User data-words 0 0 User data-words CS[2] CS[1] CS[0] Checksum ADV7181B ...
Page 54
... ADV7181B NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown in Table 69 and Table 70. NTSC closed caption data is sliced on Line 21d on even and odd fields ...
Page 55
... When GDECAD is 1, the data is output straight in 8-bit format. Rev Page 55 of 100 D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble DID 0 0 SDID Data count 0 0 User data-words 0 0 User data-words UDW padding 0x200 UDW padding 0x200 CS[2] CS[1] CS[0] Checksum ADV7181B ...
Page 56
... ADV7181B Table 73. NTSC Line Enable Bits and Corresponding Line Numbering Line Number Line[3:0] (ITU-R BT.470) Enable Bit 0 10 GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[10 GDECOL[11] ...
Page 57
... Therefore, INTRQ high impedance state after 5.0 5.5 6.0 reset must to be written to INTRQ_OP_SEL[1:0] for a logic level to be driven out from the INTRQ pin also possible to write to a register in the ADV7181B that manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ. Rev Page 57 of 100 2 COMMON I C SPACE ADDRESS 0x00 ≥ ...
Page 58
... If Interrupt Event 1 occurs and then Interrupt Event 2 occurs before the system controller has cleared or masked Interrupt Event 1, the ADV7181B does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits since more than one can be active. ...
Page 59
... PIXEL PORT CONFIGURATION The ADV7181B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. Table 78 and Table 79 summarize the various functions that the ADV7181B pins can have in different modes of operation. The ordering of components, for example CHA/B/C, can be changed ...
Page 60
... C byte means that the master reads information from the peripheral. The ADV7181B acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7181B has 249 subad- dresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress ...
Page 61
... REGISTER ACCESSES The MPU can write to or read from all of the ADV7181B’s registers, except the subaddress register, which is write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. ...
Page 62
... ADV7181B REGISTER MAPS Table 81. Common and Normal (Page 1) Register Map Details Register Name Input Control Video Selection Reserved Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value C ADI Control Power Management Status 1 ...
Page 63
... Rev Page 63 of 100 ADV7181B Subaddress Dec Hex 0x3E to 0x40 65 0x41 0x42 to 0x47 72 0x48 73 0x49 74 0x4A 75 0x4B 76 0x4C 77 0x4D ...
Page 64
... ADV7181B Register Name Drive Strength Reserved IF Comp Control VS Mode Control Table 82. Common and Normal (Page 1) Register Map Bit Names Register Name Bit 7 Bit 6 Input Control VID_SEL.3 VID_SEL.2 Video ENHSPLL Selection Reserved Output VBI_EN TOD Control Extended BT656-4 Output Control Reserved Reserved ...
Page 65
... CCAP1.4 CCAP1.3 CCAP2.5 CCAP2.4 CCAP2.3 LB_LCT.5 LB_LCT.4 LB_LCT.3 LB_LCM.5 LB_LCM.4 LB_LCM.3 LB_LCB.5 LB_LCB.4 LB_LCB.3 ADC1_SW.1 ADC1_SW.0 ADC0_SW.3 ADC2_SW.3 Rev Page 65 of 100 ADV7181B Bit 2 Bit 1 Bit 0 LMG.2 LMG.1 LMG.0 HSE.10 HSE.9 HSE.8 HSB.2 HSB.1 HSB.0 HSE.2 HSE.1 HSE.0 PCLK YCMN.2 YCMN.1 YCMN ...
Page 66
... ADV7181B Register Name Bit 7 Bit 6 Letterbox Control 1 Letterbox LB_SL.3 LB_SL.2 Control 2 Reserved Reserved Reserved SD Offset Cb SD_OFF_CB.7 SD_OFF_CB.6 SD Offset Cr SD_OFF_CR.7 SD_OFF_CR.6 SD Saturation SD_SAT_CB.7 SD_SAT_CB Saturation SD_SAT_CR.7 SD_SAT_CR.6 Cr NTSC V Bit NVBEGDEL O NVBEGDEL E Begin NTSC V Bit NVENDDEL O NVENDDEL E End NTSC F Bit NFTOGDEL O NFTOGDEL E ...
Page 67
... RQ_CLR 0x48 MPU_ STIM_INT RQ_MSKB 0x49 0x4A PAL_SW_ LK_ CHNG_Q 0x4B PAL_SW_ LK_CHNG _CLR 0x4C PAL_SW_ LK_CHNG _MSKB Rev Page 67 of 100 ADV7181B Bit 4 Bit 3 Bit 2 Bit 1 MV_INTRQ MPU_ INTRQ_ _SEL.0 STIM_INTRQ OP_SEL.1 SD_ UNLOCK_Q SD_UNLO CK_CLR SD_ UNLOCK_ MSKB WSS_ ...
Page 68
... ADV7181B Table 84. Interrupt Register Map Details Subaddress Register Bit Description 0x40 Interrupt INTRQ_OP_SEL[1:0]. Config 1 Interrupt Drive Level Select. Register Access MPU_STIM_INTRQ[1:0]. Page 2 Manual Interrupt Set Mode. Reserved. MV_INTRQ_SEL[1:0]. Macrovision Interrupt Select. INTRQ_DUR_SEL[1:0]. Interrupt Duration Select. 0x41 Reserved 0x42 Interrupt SD_LOCK_Q. Status 1 Read Only SD_UNLOCK_Q ...
Page 69
... Clears GEMD_Q bit 0 Do not clear 1 Clears CGMS_CHNGD_Q bit 0 Do not clear 1 Clears WSS_CHNGD_Q bit x Not used x Not used x Not used 0 Do not clear 1 Clears MPU_STIM_INTRQ_Q bit Rev Page 69 of 100 ADV7181B Notes These bits can be cleared or masked by Registers 0x47 and 0x48, respectively. ...
Page 70
... ADV7181B Subaddress Register Bit Description 0x48 Interrupt CCAPD_MSKB. Mask 2 GEMD_MSKB. Read/ Write CGMS_CHNGD_MSKB. Register WSS_CHNGD_MSKB. Access Page 2 Reserved. Reserved. Reserved. MPU_STIM_INTRQ_MSKB. 0x49 Raw SD_OP_50Hz. Status 3 SD 60/50Hz frame rate at output. SD_V_LOCK. Read Only Register SD_H_LOCK. Register Access Page 2 Reserved. SCM_LOCK. SECAM Lock. ...
Page 71
... Unmasks SD_OP_CHNG_Q bit 0 Masks SD_V_LOCK_CHNG_Q bit 1 Unmasks SD_V_LOCK_CHNG_Q bit 0 Masks SD_H_LOCK_CHNG_Q bit 1 Unmasks SD_H_LOCK_CHNG_Q bit 0 Masks SD_AD_CHNG_Q bit 1 Unmasks SD_AD_CHNG_Q bit 0 Masks SCM_LOCK_CHNG_Q bit 1 Unmasks SCM_LOCK_CHNG_Q bit 0 Masks PAL_SW_LK_CHNG_Q bit 1 Unmasks PAL_SW_LK_CHNG_Q bit x Not used x Not used Rev Page 71 of 100 ADV7181B Notes ...
Page 72
... ADV7181B Table 85. Common and Normal (Page 1) Register Map Details Subaddress Register Bit Description 0x00 Input INSEL[3:0]. The INSEL bits allow the Control user to select an input channel as well as the input format. VID_SEL[3:0]. The VID_SEL bits allow the user to select the input video standard ...
Page 73
... HS, VS, F three-stated 1 HS, VS, F forced active BT656-3-compatible 1 BT656-4-compatible Rev Page 73 of 100 ADV7181B Notes See TIM_OE, Address 0x04[3] and TRI_LLC, Address 0x1D[7] ITU-R BT.656. Extended range. SFL output enables encoder and decoder to be connected directly. During VBI. ...
Page 74
... ADV7181B Subaddress Register Bit Description 0x07 Autodetect E AD_PAL_EN. PAL B/G/I/H autodetect nable enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. AD_SEC525_EN. SECAM 525 autodetect enable. ...
Page 75
... NTSM-MJ Detected standard. NTSC-443 PAL-M PAL-60 PAL-B/G/H/I/D SECAM PAL-combination N SECAM 525 Color kill is active = 1 Color kill. x ADV7181B = 0x13 color striping detected 1 = detected. MV color striping type 0 = Type Type 3. MV pseudo sync detected 1 = detected. MV AGC pulses detected 1 = detected. Nonstandard line length 1 = detected ...
Page 76
... ADV7181B Subaddress Register Bit Description Analog 0x14 Reserved. Clamp CCLEN. Current clamp enable allows Control the user to switch off the current sources in the analog front. Reserved. 0x15 Digital Reserved. Clamp DCT[1:0]. Digital clamp timing Control 1 determines the time constant of the digital fine clamp circuitry. ...
Page 77
... Medium 1 0 Wide 1 1 Widest 0 0 Narrow 0 1 Medium 1 0 Medium 1 1 Wide Set as default Set to default 0 Enabled 1 Disabled 0 Use 27 MHz crystal 1 Use 28 MHz crystal 0 LLC pin active 1 LLC pin three-stated Rev Page 77 of 100 ADV7181B Notes ...
Page 78
... ADV7181B Subaddress Register Bit Description 0x27 Pixel Delay LTA[1:0]. Luma timing adjust allows Control the user to specify a timing difference between chroma and luma samples. Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples. AUTO_PDC_EN. Automatically ...
Page 79
... VS goes low in the middle of the line (odd field changes state at the start of the line (odd field) Rev Page 79 of 100 ADV7181B Notes CAGC[1:0] settings decide in which mode CMG[11:0] operates. Has an effect only if CAGC[1:0] is set to auto gain (10). ...
Page 80
... ADV7181B Subaddress Register Bit Description 0x34 HS Position HSE[10:8]. HS end allows the Control 1 positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved. 0x35 HS Position HSB[7:0] Using HSB[10:0] and HSE[10:0], the user can program the ...
Page 81
... Kill at 16 Kill at 32 Reserved 0 Set to default Rev Page 81 of 100 ADV7181B Notes Top lines of memory. All lines of memory. Bottom lines of memory. Top lines of memory. All lines of memory. Bottom lines of memory. CKE = 1 enables the color kill function and must be ...
Page 82
... ADV7181B Subaddress Register Bit Description 0x41 Resample Reserved. Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved. 0x48 Gemstar GDECEL[15:8]. See the Comments Control 1 column. 0x49 Gemstar GDECEL[7:0]. See the Comments Control 2 column. 0x4A Gemstar GDECOL[15:8]. See the Comments Control 3 column ...
Page 83
... EDTV3[7:6] are undetermined CGMS3[7:4] are undetermined Rev Page 83 of 100 ADV7181B Notes For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010. Read only status bits. EDTV3[5] is reserved for future use. ...
Page 84
... ADV7181B Subaddress Register Bit Description 0x99 CCAP1 CCAP1[7:0] (Read Only) Closed caption data register. 0x9A CCAP2 CCAP2[7:0] (Read Only) Closed caption data register. 0x9B Letterbox 1 LB_LCT[7:0] (Read Only) Letterbox data register. 0x9C Letterbox 2 LB_LCM[7:0] (Read Only) Letterbox data register. Letterbox 3 0x9D ...
Page 85
... Chroma gain = NTSC default (BT.656) 0 Set to low when manual programming 1 Not suitable for user programming 0 No delay 1 Additional delay by 1 line 0 No delay 1 Additional delay by 1 line Rev Page 85 of 100 ADV7181B Notes SETADC_sw_ man_en = 1. ...
Page 86
... ADV7181B Subaddress Register Bit Description 0xE6 NTSC V Bit NVEND[4:0]. How many lines after End l rollover to set V low. COUNT NVENDSIGN. NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field). ...
Page 87
... Auto coast mode coast mode coast mode 1 1 Reserved Rev Page 87 of 100 ADV7181B Notes 0 dB. 5 MHz NTSC filters. − PAL filters. 6 MHz + This value sets up the output coast frequency. ...
Page 88
... ADV7181B PROGRAMMING EXAMPLES EXAMPLES FOR 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 86. Mode 1 CVBS Input Register Address Register Value 0x15 0x00 0x17 0x41 0x1D 0x40 0x0F ...
Page 89
... Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page 89 of 100 ADV7181B ...
Page 90
... ADV7181B Mode 3 525i/625i YPrPb Input (Y on AIN1 AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 88. Mode 3 YPrPb Input 525i/625i Register Address Register Value 0x00 0x0A 0x1D 0x40 0x0F 0x40 0x3D 0xC3 ...
Page 91
... Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page 91 of 100 ADV7181B ...
Page 92
... ADV7181B EXAMPLES FOR 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 90. Mode 1 CVBS Input Register Address Register Value 0x15 0x00 0x17 0x41 0x3A 0x16 0x50 0x04 0xC3 0x05 ...
Page 93
... Enable manual muxing, manual mux AIN5 to ADC2 (1101). ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting. Rev Page 93 of 100 ADV7181B ...
Page 94
... ADV7181B Mode 4 CVBS Tuner Input CVBS PAL on AIN6 All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 92. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value 0x00 0x80 0x07 0x01 0x15 0x00 0x17 0x41 0x19 0xFA ...
Page 95
... ADV7181B. The location of the split should be under the ADV7181B. For this case even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). An example of a ...
Page 96
... ADV7181B DIGITAL INPUTS The digital inputs on the ADV7181B are designed to work with 3.3 V signals, and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied to the decoder. ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth ...
Page 97
... TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7181B video decoder are shown in Figure 44 and Figure 45. For a detailed schematic diagram for the ADV7181B, refer to the ADV7181B evaluation note. Figure 44. ADI Recommended Antialiasing Circuit for All Input Channels AVDD_5V R43 0 Ω BUFFER R39 ...
Page 98
... FERRITE BEAD AVDD (3.3V) 33μF 10μF AGND AGND FERRITE BEAD DVDD (1.8V) 33μF 10μF DGND DGND 100nF AIN2 100nF AIN1 100nF AIN3 AIN3 ADV7181B 100nF AIN4 100nF AIN5 100nF AIN6 AGND CAPY1 10μF 0.1μF 0.1nF CAPY2 10μF 0.1μF 0.1nF CAPC2 CML REFOUT + 0.1μF ...
Page 99
... Rev Page 99 of 100 0.30 0.25 0.18 PIN 1 INDICATOR 7.25 7. 0.25 MIN THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS. 12.00 BSC 10.00 TOP VIEW BSC SQ (PINS DOWN 0.27 0.50 0.22 BSC 0.17 ADV7181B ...
Page 100
... The ADV7181B is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering 255°C (±5°C). In addition backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220° ...