ADV7195KS Analog Devices Inc, ADV7195KS Datasheet - Page 16

• Manufacturer Part Number: ADV7195KS
• Description: IC DAC VID-HDTV 3CH-11BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7195KS

• Rohs Status: RoHS non-compliant
• Applications: HDTV, MPEG, Image Processing
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• For Use With: EVAL-ADV7195EB - BOARD EVAL FOR ADV7195
• Lead Free Status / RoHS Status: Not Compliant

ADV7195
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 20 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7195
is blanked such that a black screen is output from the DACs.
When this bit is set to “1,” pixel data is accepted at the input
pins and the ADV7195 outputs the standard set in “Output
Standard Selection” (MR01–00). This bit also must be set to
“1” to enable output of the test pattern signals.
Input Format (MR11)
It is possible to input data in 4:2:2 format or at 4:4:4 format at
27 MHz.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a crosshatch test pattern is output from
the ADV7195 (for example, in SMPTE293M, 11 horizontal
and 11 vertical white lines, four pixels wide are displayed against
a black background). The crosshatch test pattern can be used to
test monitor convergence. If this bit is set to “1,” a uniform
colored frame/field test pattern is output from the ADV7195.
The color of the lines or the frame/field is by default white but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers.
MR17
SHARPNESS
0
1
FILTER
MR17
DISABLE
ENABLE
MR16
MR16 MR15
0
0
1
1
UNDERSHOOT
LIMITER
MR15
0
1
0
1
DISABLE
–11 IRE
–6 IRE
–1.5 IRE
MR14
0
1
VBI OPEN
MR14
DISABLE
ENABLE
MR13
0
1
TEST PATTERN
HATCH/FRAME
HATCH
FIELD/FRAME
MR13
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion
during the Vertical Blanking Interval.
For this purpose Lines 13 to 42 of each frame can be used for
VBI when SMPTE293M standard is used, or Lines 6 to 43
when ITU-R.BT1358 standard is used.
Undershoot Limiter (MR15–MR16)
This control limits the Y signal to a programmable level
in the active video region.
Available limit levels are –1.5 IRE, –6 IRE, –11 IRE.
Note that this facility is only available when Interpolation is
enabled (MR36 = “1”).
Sharpness Filter (MR17)
This control bit enables or disables the Sharpness Filter Mode.
This bit must be set to “1” for any values programmed into the
Filter Gain Register to take effect. It must also be set to “1” when
Adaptive Filter mode is used.
Refer to Sharpness Filter Control and Adaptive Filter
Control section.
100 IRE
–40 IRE
0 IRE
MR12
TEST PATTERN
0
1
ENABLE
MR12
DISABLE
ENABLE
MR11
0
1
INPUT FORMAT
4:4:4 Y Cr Cb
4:2:2 Y Cr Cb
MR11
MR10
0
1
PIXEL DATA
MR10
ENABLE
DISABLE
ENABLE
–6 IRE