LTC1066-1CSW#TR Linear Technology, LTC1066-1CSW#TR Datasheet - Page 13

IC FILTER LP 8TH ORDER 18SOIC

LTC1066-1CSW#TR

Manufacturer Part Number
LTC1066-1CSW#TR
Description
IC FILTER LP 8TH ORDER 18SOIC
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1066-1CSW#TR

Filter Type
Bessel, Lowpass Switched Capacitor
Frequency - Cutoff Or Center
50kHz
Number Of Filters
1
Max-order
8th
Voltage - Supply
4.75 V ~ 16 V, ±2.375 V ~ 8 V
Mounting Type
Surface Mount
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1066-1CSW#TRLTC1066-1CSW#PBF
Manufacturer:
Linear Technology
Quantity:
135
APPLICATIONS
Aliasing
In a sampled-data system the sampling theorem says that
if an input signal has any frequency components greater
than one half the sampling frequency, aliasing errors will
appear at the output. In practice, aliasing is not always a
serious problem. High order switched-capacitor lowpass
filters are inherently band limited and significant aliasing
occurs only for input signals centered around the clock
frequency and its multiples.
Figure 6 shows the LTC1066-1 aliasing response when
operated with a clock-to-cutoff frequency ratio of 50:1.
With a 50:1 ratio LTC1066-1 samples its input twice
during one clock period and the sampling frequency is
equal to two times the clock frequency.
The figure also shows the maximum aliased output gener-
ated for inputs in the range of 2f
LTC1066-1 is programmed to produce a cutoff frequency
of 20kHz with 1MHz clock, a 10mV, 1.02MHz input signal
will cause a 10µV aliased signal at 20kHz. This signal will
be buried in the noise. Maximum aliasing will occur only
for input signals in the narrow range of 2MHz ±20kHz or
multiples of 2MHz.
Figure 7 shows the LTC1066-1 aliased response when
operated with a clock-to-cutoff frequency ratio of 100:1
(linear phase response with pin 8 to ground).
U
INFORMATION
U
CLK
±f
W
C
. For instance, if the
U
–85
–26
–60
–80
0
0
f
CLK
– 4f
f
f
C
CLK
CLK
Figure 7. Aliasing vs Frequency
f
Clock is a 50% Duty Cycle Square Wave
CLK
– f
– f
Figure 6. Aliasing vs Frequency
f
Clock is a 50% Duty Cycle Square Wave
CLK
f
C
C
f
/ f
CLK
CLK
C
f
/ f
f
CLK
CLK
= 100:1 (Pin 8 to Ground)
C
= 50:1 (Pin 8 to V
+ f
+ f
C
C
f
CLK
+ 4f
INPUT FREQUENCY
INPUT FREQUENCY
C
2f
2f
CLK
CLK
– 2.3f
+
– 4f
)
2f
2f
LTC1066-1
C
CLK
CLK
C
– f
– f
2f
2f
C
C
CLK
CLK
2f
2f
CLK
CLK
2f
+ f
+ f
2f
13
CLK
CLK
C
C
10661fa
+ 2.3f
1066-1 F06
1066-1 F07
+ 4f
C
C

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