MAX7326ATG+T Maxim Integrated Products, MAX7326ATG+T Datasheet - Page 8

• Manufacturer Part Number: MAX7326ATG+T
• Description: IC I/O EXPANDER I2C 16B 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX7326ATG+T

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
and 4 Inputs
selection logic uses AD0 to select whether pullups are
enabled for ports I2 and I3, and to set the initial logic
level for those ports, and AD2 for ports I4 and I5. The
rule is that a logic-high, SDA, or SCL connection
selects the pullups and sets the default logic state to
high. A logic-low sets the default to low (Tables 2 and
3). This means that the port configuration is correct on
power-up for a standard I
or SCL are pulled up to V+ by the external I
resistors.
The power-up default states of the 12 push-pull outputs
are set according to the I
inputs, AD0 and AD2 (Tables 2 and 3).
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7326’s supply voltage, and if that pullup supply
rises later than the MAX7326’s supply, then SDA or SCL
may appear at power-up to be connected to GND. In
applications like this, use the four address combinations
that are selected by strapping address inputs AD0 and
AD2 to V+ or ground (shown in bold in
These selections are guaranteed to be correct at power-
up, independent of SDA and SCL behavior. If one of the
Table 2. MAX7326 Address Map for Ports O0, O1, I2–I5, O6, and O7
8
CONNECTION
GND
GND
GND
GND
AD2
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
V+
V+
V+
V+
2
_______________________________________________________________________________________
C Port Expander with 12 Push-Pull Outputs
PIN
GND
GND
GND
GND
AD0
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
V+
V+
V+
V+
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DEVICE ADDRESS
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
C configuration, where SDA
2
C slave address selection
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Tables
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
2 and 3).
C pullup
O7
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O6
PORT POWER-UP DEFAULT
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
I5
other 12 address combinations is used, an unexpected
combination of pullups might be asserted until the first
I
MAX7326) is put on the bus, and an unexpected combi-
nation of ports may initialize as logic-low outputs instead
of inputs or logic-high outputs.
Port inputs switch at CMOS-logic levels as determined
by the expander’s supply voltage, and are overvoltage
tolerant to +6V, independent of the expander’s supply
voltage.
All four input ports are monitored for changes since the
expander was last accessed through the serial inter-
face. The state of the input ports is stored in an internal
“snapshot” register for transition monitoring. The snap-
shot is continuously compared with the actual input
conditions, and if a change is detected for any port
input, then an internal transition flag is set for that port.
The four port inputs are sampled (internally latched into
the snapshot register) and the old transition flags are
cleared during the I
read and write access. The previous port transition
flags are read through the serial interface as the sec-
ond byte of a 2-byte read sequence.
I4
2
Inputs
C transmission (to any device, not necessarily the
I3
I2
O1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
Port-Input Transition Detection
O0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
2
C acknowledge of every MAX7326
O7 O6
40kΩ INPUT PULLUPS ENABLED
—
—
—
—
I5
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
I3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Port Inputs
—
—
—
—
I2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
O1 O0