AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 21

• Manufacturer Part Number: AD9895KBCRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Vertical Sequence Alternation
The AD9891/AD9895 also supports line-by-line alternation of
vertical sequences within any region, as shown in Figure 23.
Table X summarizes the additional registers used to support differ-
ent alternation patterns. To create an alternating vertical pattern,
Register
VTPALT
VxSPTRFIRST
VxINVFIRST
VxSPTRSECOND
VxINVSECOND
x is the V-output from 1–4.
REV. A
HD
SEQUENCES MAY BE ALTERNATED WITHIN A REGION BY USING THE SPTRFIRST AND SPTRSECOND REGISTERS.
V1
V2
V3
V4
USE FIRST V SEQUENCES
WHEN THE VTPALT REGISTER IS LOW (NO ALTERNATION), ONLY THE FIRST LINES ARE USED.
REGION CHANGE POSITION #1
REGION CHANGE POSTION #0
REGION CHANGE POSTION #2
ONLY FIRST LINES ARE USED
ONLY FIRST LINES ARE USED
Length
1b
4b
1b
4b
1b
SECOND LINES
FIRST LINES
Figure 23. Use of Line Alteration in Vertical Sequencing
Enabled/Disabled
Sequence 0–11
High/Low
Sequence 0–11
High/Low
Range
Figure 24. Example of Line Alteration within a Region
Table X. Vertical Sequence Alternation Parameters
SINGLE FIELD (1 VD INTERVAL)
USE SECOND V SEQUENCES
–21–
Enables the Line-by-Line Alternation (1 = Enabled)
When High, the Polarity of VxSPTRFIRST Is Inverted
When High, the Polarity of VxSPTRSECOND Is Inverted
Description
SPTR for Vx Output during Each Region 0–4 for FIRST Lines
SPTR for Vx Output during Each Region 0–4 for SECOND Lines
the VxSPTRFIRST and VxSPTRSECOND Registers are pro-
grammed with the desired sequences to be alternated. The
VTPALT Register must be set HIGH for that region to use
alternation. If VTPALT is LOW, then the VxSPTRSECOND
Registers will be ignored. Figure 24 shows an example of line-
by-line alternation.
NO ALTERNATION
NO ALTERNATION
LINE-BY-LINE ALTERNATION
AD9891/AD9895
USE FIRST V SEQUENCES