AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 25

• Manufacturer Part Number: AD9895KBCRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

The frame transfer CCD also requires additional timing control
when decimating the image for Preview Mode. The
AD9891/AD9895 contain registers to independently stop the
operation of the V5–V8 outputs while the V1–V4 outputs con-
tinue to run or to stop the V1–V4 outputs, while the V5–V8
outputs remain operational. The FREEZE and RESUME Regis-
ters specify the pixel locations within each line of a region where
the V1–V4 or V5–V8 clock outputs will start to hold their state,
and where they will resume normal operation. FREEZE and
RESUME can be used in any region during the frame readout.
Register
SGPOL
SGTOG1
SGTOG2
SGACTLINE
SGSEL
SGMASK
REV. A
VSG1–VSG8
PROGRAMMABLE SETTINGS FOR EACH SEQUENCE:
1: START POLARITY OF PULSE
2: 1ST TOGGLE POSITION
STORAGE
ACTIVE
IMAGE
1b
8b
Length
12b
12b
12b
2b
AREA
AREA
VD
HD
HD
V1
V2
V3
V4
V5
V6
V7
V8
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
Sequence 0–3
8 Individual Bits
Figure 28. Example of Frame Transfer CCD Mode using V1–V8
3: 2ND TOGGLE POSITION
4: ACTIVE LINE FOR VSG PULSE WITHIN THE FIELD
Figure 29. Vertical Sensor Gate Pulse Placement
Table XIII. Sensor Gate Register Parameters
Description
Sensor Gate Starting Polarity for Sequence 0–3
First Toggle Position for Sequence 0–11
Second Toggle Position for Sequence 0–11
Line in Field where VSG1–VSG8 Are Active
Selects Sequence 0–3 for VSG1–VSG8
Masking for any of VSG1–VSG8 Signals (0 = On, 1 = Mask)
–25–
Vertical Sensor Gate (Shift Gate) Timing
With an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is not being
used, this transfer will effectively end the exposure period during the
image acquisition. From the light-shield vertical registers, the image
is then read out line-by-line by using the vertical transfer pulses
V1–V4 in conjunction with the high speed horizontal clocks.
4
1
2
3
V1 USES SEQUENCE 0
V2 USES SEQUENCE 0
V3 USES SEQUENCE 1
V4 USES SEQUENCE 1
V5 USES SEQUENCE 0
V6 USES SEQUENCE 0
V7 USES SEQUENCE 1
V8 USES SEQUENCE 1
AD9891/AD9895