AD9822JRZ Analog Devices Inc, AD9822JRZ Datasheet - Page 3

• Manufacturer Part Number: AD9822JRZ
• Description: IC CCD SIGNAL PROC 14BIT 28-SOIC
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9822JRZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 73mA
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Analog Front End Type: CCD/CIS
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 15MSPS
• Input Voltage Range: 1V
• Operating Supply Voltage (min): 3/4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Resolution: 14b
• Supply Current: 4/73mA
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• Number Of Channels: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
ANALOG SPECIFICATIONS
T
Table 1.
Parameter
MAXIMUM CONVERSION RATE
ACCURACY (ENTIRE SIGNAL PATH)
ANALOG INPUTS
AMPLIFIERS
NOISE AND CROSSTALK
POWER SUPPLY REJECTION
DIFFERENTIAL VREF (@ 25°C)
TEMPERATURE RANGE
POWER SUPPLIES
OPERATING CURRENT
MIN
3-Channel Mode with CDS
1-Channel Mode with CDS
ADC Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Offset Error
Gain Error
Input Signal Range
Allowable Reset Transient
Input Limits
Input Capacitance
Input Bias Current
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution
PGA Gain Monotonicity
Programmable Offset at Minimum
Programmable Offset at Maximum
Programmable Offset Resolution
Programmable Offset Monotonicity
Total Output Noise @ PGA Minimum
Total Output Noise @ PGA Maximum
Channel-to-Channel Crosstalk @ 6 MHz
AVDD = 5 V ± 0.25 V
CAPT to CAPB (2 V ADC Full-Scale Range)
Operating
Storage
AVDD
DRVDD
AVDD
DRVDD
Power-Down Mode Current
INL @ 6 MHz
DNL @ 6 MHz
No Missing Codes @ 6 MHz
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS mode, f
2
1
2
1
ADCCLK
Rev. B | Page 3 of 20
= 15 MHz, f
Min
15
12.5
−1.0
14
−240
−1.4
AVSS − 0.3
0.94
0
−65
4.75
3.0
CDSCLK1
= f
CDSCLK2
Typ
14
−17.0/+3.5
−10.5/+1.5
−0.65/+0.75
−0.6/+0.65
14
−19
+3.5
2.0
1.0
10
10
1
5.7
64
Guaranteed
−350
+350
512
Guaranteed
1.5
6.0
<1
0.063
1.0
5.0
5.0
73
4
150
= 5 MHz, PGA gain = 1, unless otherwise noted.
Max
+1.1
+200
+6.9
AVDD + 0.3
0.9
1.06
+70
+150
5.25
5.25
Bits
LSB
LSB
V p-p
V
pF
Steps
Steps
LSB rms
LSB rms
LSB
mA
mA
AD9822
Unit
MSPS
MSPS
LSB
LSB
Bits
Bits
mV
% FSR
V
nA
V/V
V/V
mV
mV
% FSR
V
°C
°C
V
V
µA