PI7C9X20303ULAZPE Pericom Semiconductor, PI7C9X20303ULAZPE Datasheet - Page 33

• Manufacturer Part Number: PI7C9X20303ULAZPE
• Description: IC PCIE PACKET SWITCH 132VQFN
• Manufacturer: Pericom Semiconductor
• Series: UltraLo™r

Specifications of PI7C9X20303ULAZPE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 132-VQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.4
7.2.5
7.2.6
August 2009 – Revision 1.1
Pericom Semiconductor
PRIMARY STATUS REGISTER – OFFSET 04h
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
BIT
15:11
BIT
18:16
19
20
21
22
23
24
26:25
27
28
29
30
31
BIT
7:0
BIT
15:8
23:16
31:24
FUNCTION
Reserved
FUNCTION
Reserved
Interrupt Status
Capabilities List
66MHz Capable
Reserved
Fast Back-to-Back
Capable
Master Data Parity
Error
DEVSEL# timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity Error
FUNCTION
Revision
FUNCTION
Programming
Interface
Sub-Class Code
Base Class Code
TYPE
TYPE
TYPE
TYPE
RWC
RWC
RWC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 33 of 77
DESCRIPTION
Reset to 0b.
DESCRIPTION
Reset to 000b.
Indicates that an INTx Interrupt Message is pending internally to the device.
In the Switch, the forwarding of INTx messages from the downstream device
of the Switch port is not reflected in this bit. Must be hardwired to 0b.
Set to 1 to enable support for the capability list (offset 34h is the pointer to
the data structure).
Reset to 1b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the primary side of the port in a Switch.
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request on the primary side
using the Completer Abort Completion Status.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status on the primary side.
Reset to 0b.
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status on primary side.
Reset to 0b.
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Command register is 1.
Reset to 0b.
Set to 1 whenever the primary side of the port in a Switch receives a Poisoned
TLP.
Reset to 0b.
DESCRIPTION
Indicates revision number of device. Hardwired to 03h.
DESCRIPTION
Read as 00h to indicate no programming interfaces have been defined for
PCI-to-PCI Bridges.
Read as 04h to indicate device is a PCI-to-PCI Bridge.
Read as 06h to indicate device is a Bridge device.
3Port-3Lane PCI Express® Switch
UltraLo
PI7C9X20303UL
Datasheet
TM
Family