PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 30

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.20. POWER MANAGEMENT DATA REGISTER – OFFSET 84h
6.2.21. PPB SUPPORT EXTENSIONS – OFFSET 84h
6.2.22. PM DATA REGISTER – OFFSET 84h
6.2.23. MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
31:27
BIT
1:0
2
3
7:4
8
12:9
14:13
15
BIT
21:16
22
23
BIT
31:24
BIT
7:0
FUNCTION
Enhanced
Capability ID
FUNCTION
PME# Support
FUNCTION
Power State
Reserved
No_Soft_Reset
Reserved
PME# Enable
Data Select
Data Scale
PME status
FUNCTION
Reserved
B2_B3 Support for
D3
Bus Power / Clock
Control Enable
FUNCTION
PM Data Register
HOT
09-0088
TYPE
TYPE
TYPE
TYPE
TYPE
RO
RO
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Read as 05h to indicate that this is Message Signaled Interrupt
capability register.
DESCRIPTION
Read as 01000b to indicate the I/O bridge supports the forwarding of
PME# message in all power states. The default value may be
changed by auto-loading from EEPROM.
DESCRIPTION
Reset to 000000b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
DESCRIPTION
PM Data Register.
Reset to 00h
DESCRIPTION
Indicates the current power state of the I/O bridge. Writing a value of
D0 causes a hot reset without asserting PEREST_L when the
previous state was D3.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
Read as 0b.
When set, this bit indicates that I/O bridge transitioning from D3hot
to D0 does not perform an internal reset.
When clear, an internal reset is performed when power state transits
from D3hot to D0. The default value may be changed by
auto-loading from EEPROM.
Reset to 0b.
Read as 0h.
When asserted, the I/O bridge will generate the PME# message.
Reset to 0b.
Select data registers.
Reset to 0h.
Read as 00b.
Indicates that the PME# message is pending internally to the I/O
bridge.
Reset to 0b.
PCI Express® Quad UART
PI7C9X7954
Datasheet