DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 23

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev: 063008
RXD[0]/RXD1[0],
RXD[1]/RXD1[1],
RXD[2]/RXD1[2],
RXD[3]/RXD1[3],
RXD[4]/RXD2[0],
RXD[5]/RXD2[1],
RXD[6]/RXD2[2],
RXD[7]/RXD2[3]
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
TXD[0]/TXD1[0],
TXD[1]/TXD1[1],
TXD[2]/TXD1[2],
TXD[3]/TXD1[3],
TXD[4]/TXD2[0],
TXD[5]/TXD2[1],
TXD[6]/TXD2[2],
TXD[7]/TXD2[3]
RX_CLK1,
TX_CLK1,
RX_CLK2
TX_CLK2
NAME
PACKAGE PINS
H13,
N15,
R15,
G14,
H14,
N16,
M16,
G16,
M15,
K15,
P15,
F13,
F14,
J13,
J15,
L15,
T15
K16
N13
256
T16
H10,
H11,
K10,
L10,
L11,
J10,
J11,
144
K11
L12
H8,
H9,
J12
K8,
J8,
J9,
L8,
L9,
K9
TYPE
IO
IO
O
I
Transmit Data 0 through 7(GMII Mode). TXD[0:7] is presented
synchronously with the rising edge of TX_CLK1. TXD[0] is the least
significant bit of the data. When TX_EN1 is low the data on TXD should
be ignored.
MAC 1 Transmit Data 0 through 3(MII Mode – TXD1[0:3]). Four bits of
data TXD1[0:3] presented synchronously with the rising edge of
TX_CLK1.
MAC 1 Transmit Data 0 through 1(RMII Mode – TXD1[0:1]). Two bits of
data TXD1[0:1] presented synchronously with the rising edge of
TX_CLK1.
MAC 2 Transmit Data 0 through 3(MII Mode– TXD2[0:3]).Four bits of
data TXD2[0:3] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:3] is only available on devices with two
Ethernet ports.
MAC 2 Transmit Data 0 through 1(RMII Mode– TXD2[0:1]). Two bits of
data TXD2[0:1] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:1] is only available on devices with two
Ethernet ports.
MAC 1 Receive Data 0 through 7(GMII Mode). Eight bits of received
data, sampled synchronously with the rising edge of RX_CLK. For every
clock cycle, the PHY transfers 8 bits to the device. RXD[0] is the least
significant bit of the data. Data is not considered valid when RX_DV is
low.
MAC 1 Receive Data 0 through 3(MII Mode – RXD1[0:3]). Four bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
MAC 1 Receive Data 0 through 1(RMII Mode – RXD1[0:1]). Two bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
MAC 2 Receive Data 0 through 3(MII Mode – RXD2[0:3]): Four bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
MAC 2 Receive Data 0 through 1(RMII Mode – RXD2[0:1]). Two bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
Receive Clock 1 (GMII). 125MHz clock. This clock is used to sample the
RXD[7:0] data.
Receive Clock 1 (MII). Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY.
Receive Clock 2 (MII Only). Timing reference for RX_DV2, RX_ERR2 and
RXD2[3:0], which are clocked on the rising edge. RX_CLK2 frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY. Note that RX_CLK2 is
only available on devices with two Ethernet ports.
Transmit Clock 1 (MII). Timing reference for TX_EN1 and TXD1[3:0].
The TX_CLK1 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Sourced from REF_CLK Input.
Transmit Clock 2 (MII Only). Timing reference for TX_EN2 and TXD2[3:0].
The TX_CLK2 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Note that TX_CLK2 is only available on devices with two Ethernet
ports. Sourced from REF_CLK Input.
GMII/MII/RMII PORT
FUNCTION
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