BD6762FV-E2 Rohm Semiconductor, BD6762FV-E2 Datasheet
BD6762FV-E2
Specifications of BD6762FV-E2
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BD6762FV-E2 Summary of contents
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... BD6761FS,BD6762FV ●Description This product is the motor predriver for high-side/low-side N-channel MOS-FET drive, which has the built-in booster (step-up) circuit. BD6761FS uses the drive type controlled by the servo signal input from outside and BD6762FV incorporates a servo circuit (Speed discriminator + PLL servo). ●Features ...
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... BD6761FS,BD6762FV ●Electrical Characteristics BD6761FS (Unless otherwise specified, Ta=25°C, VCC=24.0V) Parameter Overall Circuit current VREG voltage Hall amp Input bias current In-phase input voltage range Input level PWM High CFE voltage Low CFE voltage CFE oscillating frequency PWM on duty offset Torque amplifier ...
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... BD6761FS,BD6762FV BD6762FV (Unless otherwise specified, Ta=25°C, VCC=24V) Parameter Overall Circuit current 1 Circuit current 2 VREG voltage Low voltage protection level Low voltage protection hysteresis level VUVHYS Hall amp Input bias current In-phase input voltage range Input level PWM High CFE voltage ...
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... BD6761FS,BD6762FV BD6762FV (Unless otherwise specified, Ta=25°C, VCC=24 V) Parameter Start/Stop High-level ST/SP input voltage Low-level ST/SP input voltage High-level ST/SP input current Low-level ST/SP input current Forward rotation/Reverse rotation High-level FR input voltage Low-level FR input voltage High-level FR input current Low-level FR input current 120° ...
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... Fig.8 BD6762FV Power Dissipation Reduction Reduced by 8.8 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm 1.6 mm)/℃で軽減。 5/22 Technical Note 40.0 35.0 -35℃ 30.0 25.0 75℃ ...
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... BD6761FS,BD6762FV ●Block Diagram, Application Circuit Diagram, and Pin Function 1)BD6761FS ⑮ Output FET gate voltage stabilization resistor See P.19/22. ② ③ Capacitor, diode for the protection between the output FET drain and source MOS See P. 18/22. FET 0.1µF MOS M FET 0.1µ ...
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... REGURATOR CFE TRIANGULAR OSCILLATOR RFE VCC 5k (2kΩ ~ 10kΩ) HU+ 0.01µF HU HU- HV+ 0.01µF HALL COMP HV HV- HW+ 0.01µF HW HW- 2k (1kΩ ~ 5kΩ) Fig.10 BD6762FV Block Diagram Function No. Pin name 21 ST/ 120/SL 25 FGIN+ 26 FGIN- 27 FGOUT 28 FGSOUT FGS output pin 29 CLKIN 30 ...
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... BD6761FS,BD6762FV ●I/O Logic 1)BD6761FS Forward rotation (F/R=Low) Input conditions 15 17 Pin No. HU+ HV+ Condition Condition Condition Condition Condition Condition Condition Condition Condition Condition Condition Condition Reverse rotation (F/R=High) Input conditions 15 17 Pin No. HU+ HV+ Condition Condition Condition Condition Condition Condition Condition Condition Condition 9 ...
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... BD6761FS,BD6762FV ACC, DEC Input conditions 21 22 Pin No. DEC ACC Condition Condition Condition Condition ＜Input conditions＞ ACC, DEC input conditions H：2.2V L：0.8V ＜Output criteria＞ ○CPOUT RCP=13.5kΩ, CPOUT=3V High: Current outflow more than 140μA from CPOUT pin Low: Current inflow more than 140μA to CPOUT pin OPEN: CPOUT pin current -10μ ...
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... BD6761FS,BD6762FV 2)BD6762FV Forward rotation (F/R=Low), 120° (120/SL=High) Input conditions 15 17 Pin No. HU+ HV+ Condition Condition Condition Condition Condition Condition Reverse rotation (F/R=High), 120° (120/SL=High) Input condition 15 17 Pin No. HU+ HV+ Condition Condition Condition Condition Condition Condition ST/SP Mode OPEN or High Standby ...
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... SINU, SINV, and SINW are the internal IC signals synthesized by the Hall amplifier. 2) BD6762FV Hall signal HU+ HU- HV- HV+ HW- HW+ 120° 120° slope Fig.12 BD6762FV I/O Timing Chart www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/22 Technical Note 2010.06 - Rev.A ...
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... BD6761FS,BD6762FV ●I/O Circuit Diagram 1) BD6761FS ○High-side gate VG VG UHG (pin3) VHG (pin5) WHG (pin7) 100kΩ ○Booster VREG 8.5V VCC CP1 CP2 30Ω (pin2) (pin32) ○RCP, RFE pins VREG 33kΩ VCC 26kΩ 30Ω RCP (pin23) ○Peak hold VCC 200Ω ...
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... BD6761FS,BD6762FV 2)BD6762FV ○RF pin VCC RF (pin2) 1kΩ ○CFE pin VREG 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ 30Ω ○ HU+, HV+, HW+, HU-, HV-, HW- pins VREG VREG VCC HU+(pin15) 5kΩ HV+(pin17) HW+(pin19) ○CLKIN 5V VCC 50kΩ 5kΩ CLKIN (pin29) ○ FGSOUT pin VREG FGSOUT (pin28) 20kΩ ...
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... BD6761FS,BD6762FV ○ INTIN pin VCC 1kΩ INTIN (pin33) ○ LP pin VREG 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ ○ VG, CP2, CP1 pins VCC 8.5V 30Ω CP1 (pin40) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. ○INTOUT pin VREG VREG 90Ω 90Ω INTOUT ○ ...
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... Current limit operation When the CL voltage (BD6761FS) and RF voltage (BD6762FV) become the current limit voltage, the current limit circuit operates and works to limit PWM on_dutty. It also turns off the current limit circuit (current limit clear) at the peak of PWM triangular waveform and makes the current flow again. Output current Iomax at this time are shown in the table. ...
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... Short brake (BD6761FS and BD6762FV) BD6761FS operates the short brake action with the ACC and DEC pins set to low, and BD6762FV does with the SB pin set to OPEN or high. At the time of short brake, the high-side gate is turned off and the low-side is turned on. At the time of short brake operating, the current flows to the output FET, which is decided by the motor's counter electromotive voltage and coil impedance ...
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... CLKIN acquired in PLL block and the FG are integrated together and smoothed to become the DC voltage. This smoothed signal determines the PWM on-duty. 14) Speed lock detection circuit (BD6762FV) When the motor speed is within 6.25% range to the CLKIN signal (29 pin output to the LD pin (36 pin) output. ...
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... VG and VCC. The following constants are appropriate. BD6761FS Cfe=1000pF, Rfe=50kΩ, fo=16.5kHz(TYP.) BD6762FV Cfe=1000pF, Rfe=20kΩ, fo=16.0kHz(TYP.) Connect to the transistor base via 1k resistor (base current limit) from the VREG pin. Connect the transistor collector to VCC, the emitter to the hall element via R1. ...
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... IC output and external MOSFET gate. ⑯Peak hold setting capacitor (BD6761FS) Charges the peak hold on the voltage at the current detection pin CL. ⑰Motor locking detection time setting capacitor (BD6762FV) Motor locking detection time which is connected to the LP pin and the count number CLP (Preset value: 96) of the internal counter ...
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... TSD circuit is assumed. TSD on temperature [°C] BD6761FS BD6762FV (10) PWM drive Voltage between the output FET drain and source may exceed the absolute maximum ratings due to the fluctuation of VCC at the time of PWM driving. If there is the threat of this problem recommended to take physical countermeasures for safety such as inserting the capacitor between the VCC pin of FET and the detection resistor pin ...
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... BD6761FS,BD6762FV (12) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in Fig. 14, ○ ...
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... BD6761FS,BD6762FV ●Ordering part number Part No. Part No. 6761 6762 SSOP-A32 13.6 ± 0.2 (MAX 13.95 include BURR 0.36 ± 0.1 0.1 0.8 SSOP-B40 13.6 ± 0.2 (MAX 13.95 include BURR 0.65 0.22 ± 0.1 0.08 M www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. ...
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