SC4525CSETRT Semtech, SC4525CSETRT Datasheet - Page 14

• Manufacturer Part Number: SC4525CSETRT
• Description: IC BUCK ADJ 3A 8SOIC
• Manufacturer: Semtech
• Series: -r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of SC4525CSETRT

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1 V ~ 26.88 V
• Current - Output: 3A
• Frequency - Switching: 300kHz ~ 1.3MHz
• Voltage - Input: 3 V ~ 28 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SC4525CSETR

Applications Information (Cont.)
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
Therefore, the procedure of the voltage loop design for
the SC4525C can be summarized as:
(1) Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, F
10% and 20% of the switching frequency. At F
required compensator gain, A
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at F
(3) Place the compensator zero, F
20% of the crossover frequency, F
(4) Use the compensator pole, F
F
(5) Then, the parameters of the compensation network
can be calculated by
where g
Z
.
-30
-30
-60
-60
60
60
30
30
0
0
1K
1K
R
R
C
C
C
C
A
A
A
A
R
R
C
C
C
C
G
G
R
R
C
C
C
C
V
V
A
A
A
A
V
V
V
V
V
V
7
7
o
o
Figure 8. Bode plots for voltage loop design
C
C
C
C
5
5
8
8
c
c
7
7
7
7
C
C
C
C
5
5
8
8
o
o
c
c
PWM
PWM
5
5
8
8
m
=0.3mA/V is the EA gain of the SC4525C.
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
. 0
. 0
1 (
1 (
−
−
−
−
10
10
2
2
2
2
. 0
. 0
1 (
1 (
−
−
−
−
2
2
2
2
2
2
2
2
≈
≈
g
g
⋅ π
⋅ π
⋅ π
⋅ π
⋅ π
⋅ π
20
20
20
20
28
28
⋅ π
⋅ π
π
π
π
π
20
20
20
20
28
28
+
+
G
G
+
+
10
10
m
m
10
10
A
A
20
20
F
F
Fp
Fp
F
F
C
C
CA
CA
16
16
600
600
1
1
1
1
/ s
/ s
16
16
600
600
/ s
/ s
1 Z
1 Z
P
P
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
1
1
⋅
⋅
R
R
15
15
15
15
log
log
log
log
10
10
20
20
log
log
log
log
10
10
20
20
⋅
⋅
10K
10K
R
R
R
R
G
G
9 .
9 .
G
G
ω
ω
9 .
9 .
R
R
⋅
⋅
ω
ω
⋅
⋅
10
10
7
7
PWM
PWM
10
10
7
7
PWM
PWM
⋅
⋅
p
p
S
S
⋅
⋅
p
p


 
 








−
−


 
 








−
−
10
10
1 ( )
1 ( )
10
10
1 ( )
1 ( )
3
3
3
3
,
,
G
G
28
28
Fz1
Fz1
G
G
28
28
3
3
1
1
3
3
1
1
1 (
1 (
=
=
CA
CA
1 (
1 (
1
1
=
=
CA
CA
1
1
3
3
1
1
⋅
⋅
3
3
+
+
1
1
⋅
⋅
+
+
FREQUENCY (Hz)
FREQUENCY (Hz)
⋅
⋅
22
22
22
22
⋅
⋅
22
22
22
22
R
R
R
R
⋅
⋅
+
+
⋅
⋅
+
+
6
6
/ s
/ s
6
6
/ s
/ s
22
22
22
22
S
S
S
S
1 .
1 .
R s
R s
1 .
1 .
R s
R s
.
.
1 .
1 .
1
1
.
.
1 .
1 .
1
1
k 3
k 3
⋅
⋅
k 3
k 3
C
⋅
⋅
ω
ω
ω
ω
1 .
1 .
. In typical applications with
1 .
1 .
100K
100K
2
2
⋅
⋅
Fc
Fc
ESR
ESR
2
2
⋅
⋅
ESR
ESR
⋅
⋅
⋅
⋅
n
n
10
10
n
n
10
10
π
π
ω
ω
10
10
π
π
10
10
P1
Q
Q
⋅
⋅
Q
Q
⋅
⋅
F
F
10
10
F
F
p
p
C
C
10
10
1
1
C
C
, to cancel the ESR zero,
1
1
C
+
+
C
C
−
−
+
+
C
C
−
−
.
3
3
≈
≈
O
O
3
3
O
O
3
3
C
C
Z1
3
3
C
C
C
s
s
Fp1
Fp1
s
s
)
)
3
3
Fz
Fz
)
)
3
3
R
R
=
=
can be estimated by
O
O
, between 10% and
=
=
⋅
⋅
O
O
2
2
⋅
⋅
2
2
2
2
1
1
C
C
=
=
2
2
=
=
. 0
. 0
/
/
. 0
. 0
⋅
⋅
/
/
⋅
⋅
⋅ π
⋅ π
O
O
12
12
⋅ π
⋅ π
12
12
V
V
ω
ω
Fsw/2
Fsw/2
ω
ω
V
V
V
V
45
45
V
V
45
45
FB
FB
,
,
FB
FB
O
O
2
2
n
n
1M
1M
2
2
n
n
O
O
80
80
80
80
pF
pF
pF
pF
)
)
)
)
nF
nF
nF
nF


 
 




 
 


⋅
⋅
⋅
⋅
C
10
10
10
10
, between
C
, find the
(9)
1
1
1
1
3
3
3
3
⋅
⋅
⋅
⋅
ω
ω
22
22
22
22
Z
Z
10M
10M
=
=
⋅
⋅
⋅
⋅
10
10
10
10
R
R
ESR
ESR
−
−
−
−
1
1
6
6
6
6
C
C
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/3A converter with 47uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator zero and pole at F
(20% of F
required compensator gain at F
Then the compensator parameters are
Select R
Compensator parameters for various typical applications
are listed in Table 5. A MathCAD program is also available
upon request for detailed calculation of the compensator
parameters.
Thermal Considerations
For the power transistor inside the SC4525C, the
conduction loss P
circuit loss P
where V
switching time of the NPN transistor (see Table 4).
⋅
⋅
⋅
⋅
A
O
O
1
1
3
3
1
1
3
3
C
,
,
0 .
0 .
3 .
3 .
0 .
0 .
3 .
3 .












P
P
P
P
P
P
P
P
P
P
P
P
20
=
=
=
=
C
C
BST
BST
D
D
IND
IND
TOTAL
TOTAL
SW
SW
7
BST
=16.9k, C
15
15
15
15
=
=
=
=
log
is the BST supply voltage and t
R
=
=
C
C
C
=
=
=
=
D
D
1 (
1 (
), and F
9 .
9 .
9 .
9 .
7
BST,
5
8
=
=
1
1
1 (
1 (
2
2
D
D
⋅
⋅
18.5
=
=
=
dB
dB
−
−
dB
dB
V
V
P
P
1 .
1 .
⋅
⋅
⋅
⋅
can be estimated as follows:
CESAT
CESAT
2
2
C
C
) D
) D
t
t
V
V
0.3
⋅ π
S
S
BST
BST
⋅ π
~
~
. 3
10
+
+
C
5
⋅
⋅
1
⋅
⋅
=0.68nF, and C
, the switching loss P
1
1
53
16
P
P
V
V
600
⋅
V
V
14
20
10
⋅
⋅
⋅
⋅
D
D
3 .
3 .
P1
SW
SW
IN
IN
1 .
I
I
40
40
10
⋅
O
O
=600kHz. From Equation (9), the
I
I
⋅
⋅
I )
I )
O
O
−
10
⋅
⋅
⋅
I
I
⋅
⋅
3
+
+
I
I
O
O
10
O
O
3
2
2
O
O
3
P
P
1
=
1
⋅
⋅
3
BST
BST
⋅
⋅
⋅
2
F
F
⋅
16.9
16.9
R
R
16.9
SW
SW
DC
DC
80
+
+
C
P
P
⋅
k
⋅
10
10
is
10
Q
Q
8
=22pF for the design.
1
3
3
3
47
P
P
=
=
Q
Q
15.7
. 0
10
SW
=
=
S
589
is the equivalent
, and bootstrap
V
V
6
IN
IN
pF
1
3
nF
⋅
⋅
0 .
3 .
2
2
mA
mA
(10)
Z1
14.1
=16kHz
dB
14