DS33W41+ Maxim Integrated Products, DS33W41+ Datasheet - Page 275

• Manufacturer Part Number: DS33W41+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W41+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8.7 MAC Registers
The control registers related to the control of the individual MACs are shown in the following Table. The device
keeps statistics for the packet traffic sent and received. Note that the addresses listed are the indirect addresses
that must be provided to SU.MAC1RADH/SU.MAC1RADL or SU.MAC1AWH/SU.MAC1AWL.
Register Name:
Register Description:
Register Address:
0000h:
Default
0001h:
Default
0002h:
Default
0003h:
Default
Bit 23: Watchdog Disable (WDD) - When set to 1, the watchdog timer on the receiver is disabled. When equal to
0, the MAC allows only 2048 bytes of data per frame.
Bit 22: Jabber Disable (JD) - When set to 1, the transmitter’s jabber timer is disabled. When equal to 0, the MAC
allows only 2048 bytes to be transmitter per frame.
Bit 21: Frame Burst Enable (FBE) – When set to 1, the MAC allows frame bursting during transmission in half-
duplex mode.
Bit 20: Jumbo Frame Enable (JFE) - When set to 1, the MAC allows the reception of frames up to 9018 bytes in
length without reporting a giant frame error in the receive frame status register. Frames between 9018 and 10240
bytes in length are passed with a giant frame error indication. Jabber Disable and Watchdog Disable bits should be
set to 1 to transmit and receive jumbo frames. This bit should be cleared when operating in full-duplex mode.
Bit 15: GMII / MII Selection (GMIIMIIS)
Bit 14: Endian Mode (EM) - When set to 1, the MAC operates in Big-Endian Mode. When equal to 0, the MAC
operates in Little-Endian Mode. The Endian mode selection is applicable only for the transmit and receive data
paths.
Bit 13: Disable Receive Own (DRO) - When set to 1, the MAC disables the reception of frames while TX_EN is
asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared
when operating in full-duplex mode.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = GMII mode
1 = MII/RMII mode
Reserved
GMIIMIIS
ACST
Bit 31
Bit 23
Bit 15
WDD
Bit 7
0
0
0
0
BOLMT1
Reserved
Bit 30
Bit 22
Bit 14
Bit 6
EM
JD
0
0
0
0
SU.MACCR
MAC Control Register
0000h (indirect)
BOLMT0
Reserved
Bit 29
Bit 21
Bit 13
Bit 5
DRO
FBE
0
0
0
0
Reserved
Bit 28
Bit 20
Bit 12
Bit 4
JFE
DC
LM
0
0
0
0
Reserved
Reserved
Bit 27
Bit 19
Bit 11
Bit 3
DM
TE
0
0
0
0
Reserved
Reserved
Reserved
Bit 10
Bit 26
Bit 18
Bit 2
RE
0
0
0
0
Reserved
Reserved
Reserved
DRTY
Bit 25
Bit 17
Bit 9
Bit 1
0
0
0
0
Reserved
Reserved
Reserved
275 of 375
Bit 24
Bit 16
APST
Bit 0
Bit 8
0
0
0
0