DS33W41+ Maxim Integrated Products, DS33W41+ Datasheet - Page 83

• Manufacturer Part Number: DS33W41+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W41+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.19.1 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown Figure 8-17. The read/write control of the MII Management is accomplished through the indirect
SU.GMIIA MII Management Address Register and data is passed through the indirect SU.GMIID Data Register.
These indirect registers are accessed through the MAC Control Registers defined in Table 8-14. The MDC clock is
internally generated and runs at 1.67MHz. Note that the device provides a single MII Management port, and all
control registers for this function are located in MAC 1.
Figure 8-17. MII Management Frame
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
READ
WRITE
Preamble
111...111
111...111
32 bits
2 bits
Start
01
01
2 bits
Opco
de
10
01
Phy Adrs
PHYA[4:0]
PHYA[4:0]
5 bits
PHYR[4:0]
PHYR[4:0]
Phy Reg
5 bits
Aroun
2 bits
Turn
ZZ
10
d
ZZZZZZZZZ
PHYD[15:0]
bits
Data
16
Idle
Bit
Z
Z
1
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