DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 174

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0BDh:
Default
Register Name:
Register Description:
Register Address:
0BCh:
Default
NOTE: This is a real-time status register. Usefulness is limited to single frame transmissions for system
debugging. Most applications will be better served by monitoring the MAC Management Counter (MMC)
registers rather than polling these bits.
Bit 15: LAN Transmit Error Detected (LTED) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission attempt. Indicates Jaber Timeout, Frame Flushed, Loss of Carrier, No
Carrier, Late Collision, Excessive Collisions, or Excessive Deferral.
Bit 14: LAN Transmit Jabber Timeout (LTJTO) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Jaber Timeout.
Bit 13: LAN Transmit Frame Flushed (LTFF) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the frame being flushed by a software reset.
Bit 11: LAN Transmit Loss of Carrier (LTLOC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Loss of Carrier.
Bit 10: LAN Transmit No Carrier Present (LTNCP) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to the lack of a Carrier.
Bit 9: LAN Transmit Late Collision (LTLC) This real-time status bit is set to 1 when the transmit MAC encounters
an error during a transmission due to a Late Collision.
Bit 8: LAN Transmit Excessive Collisions (LTEC) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive (>16) Collisions.
Bits 3-6: LAN Transmit Collision Count (LTCC[3:0]) These real-time status bits indicate the number collisions
encountered while attempting to transmit the current frame.
Bit 2: LAN Transmit Excessive Deferral (LTEXD) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to Excessive Deferral.
Bit 1: LAN Transmit Underflow Error (LTUFE) This real-time status bit is set to 1 when the transmit MAC
encounters an error during a transmission due to data underflow.
Bit 0: LAN Transmit Deferred (LTDEF) This real-time status bit is set to 1 when the transmit MAC is deferring
transmission due to carrier availability. Only valid in half-duplex mode.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 15
LTED
Bit 7
0
0
-
LTJTO
LTCC3
Bit 14
Bit 6
0
0
SU.LP2XS
LAN Port 2 Transmit Status
0BCh
LTCC2
Bit 13
LTFF
Bit 5
0
0
LTCC1
Bit 12
Bit 4
0
0
-
LTLOC
LTCC0
Bit 11
Bit 3
0
0
LTNCP
LTEXD
Bit 10
Bit 2
0
0
LTUFE
LTLC
Bit 9
Bit 1
0
0
174 of 375
LTDEF
LTEC
Bit 8
Bit 0
0
0