AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet
AD9396KSTZ-100
Specifications of AD9396KSTZ-100
Related parts for AD9396KSTZ-100
AD9396KSTZ-100 Summary of contents
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FEATURES Analog/DVI dual interface Supports high bandwidth digital content protection RGB-to-YCbCr 2-way color conversion Automated clamping level adjustment 1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats Analog interface 8-bit triple ADC 150 MSPS maximum conversion ...
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AD9396 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Analog Interface Electrical Characteristics............................... 3 Digital Interface Electrical Characteristics ............................... 4 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels ........................................................... ...
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... Full IH Input Current, Low (I ) Full IL Input Capacitance 25°C DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle, DATACK Full Output Coding AD9396KSTZ-100 Test Level Min Typ Max 8 I –0.6 +1.6/–1.0 I ±1.0 ±2.1 Guaranteed VI 0.5 VI 1.0 V 100 V 0 ...
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... IV 1.7 1.8 1.9 VI 260 300 100 1.1 1.4 VI 130 V 330 AD9396KSTZ-100 Test Level Conditions Min VI 2 Output drive = high IV Output drive = low IV Output drive = high IV Output drive = low IV Output drive = high IV Output drive = low IV Output drive = high IV Output drive = low IV 75 Rev ...
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... L IV Output drive = high Output drive = low Output drive = high Output drive = low Rev Page AD9396KSTZ-100 AD9396KSTZ-150 Min Typ Max Min Typ 3.15 3.3 3.47 3.15 3.3 1.7 3.3 347 1.7 3.3 1.7 1.8 1.9 1.7 1.8 1.7 1.8 1.9 1.7 1 ...
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AD9396 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 PIN 1 GREEN 7 2 GREEN 6 3 GREEN 5 4 GREEN 4 5 GREEN 3 6 GREEN 2 7 GREEN 1 8 GREEN GND 11 BLUE 7 ...
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AD9396 Pin Type Pin No. OUTPUTS 24, 25, 26, 27 REFERENCES 57 POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL 83 82 HDCP 49 50 ...
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Mnemonic Description RxC+ Digital Data Clock True. RxC− Digital Data Clock Complement. This clock pair receives a TMDS clock at 1× pixel data rate. HSYNC 0 Horizontal Sync Input Channel 0. HSYNC 1 Horizontal Sync Input Channel 1. These inputs ...
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AD9396 Mnemonic Description DATA ENABLE Data Enable that defines valid video. Can be received in the signal or generated by the AD9396. CTL Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. ...
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DESIGN GUIDE GENERAL DESCRIPTION The AD9396 is a fully integrated solution for capturing analog RGB or YUV signals and digitizing them for display on flat panel monitors, projectors, or PDPs. In addition, the AD9396 has a digital interface for receiving ...
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AD9396 This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9396. The key to clamping is to identify a portion (time) of the signal when the graphic system is known ...
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Note that the SOG signal is always negative polarity. For more detail on setting the SOG threshold and other SOG-related functions, see the Sync Processing section. 47nF R AIN 47nF B AIN 47nF G AIN 1nF SOG Figure 4. Typical ...
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AD9396 Power Management The AD9396 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power ...
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TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9396, which must be flushed before ...
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AD9396 Sync Processing The inputs of the sync processing section of the AD9396 are combinations of digital HSYNCs and VSYNCs, analog sync-on- green, or sync-on-Y signals, and an optional external coast signal. From these signals, it generates a precise, jitter-free ...
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Sync Slicer The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input. The sync signal is extracted in a two-step process. First, the ...
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AD9396 HSYNC Filter and Regenerator The HSYNC filter is used to eliminate any extraneous pulses from the HSYNC or SOGIN inputs, outputting a clean, low jitter signal that is appropriate for mode detection and clock generation. The HSYNC regenerator is ...
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VSYNC Filter and Odd/Even Fields The VSYNC filter is used to eliminate spurious VSYNCs, maintain a consistent timing relationship between the VSYNC and HSYNC output signals, and generate the odd/even field output. The filter works by examining the placement of ...
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AD9396 The functional diagram for a single channel of the CSC, as shown in Figure 13, is repeated for the remaining G and B channels. The coefficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4. ...
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SERIAL REGISTER MAP The AD9396 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. ...
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AD9396 Hex Read/Write Default Address or Read Only Bits Value 0x12 Read/Write [7] 1******* [6] *0****** [5] **1***** [4] ***0**** [3] ****1*** [2] *****0** [1] ******0* [0] *******1 0x13 Read/Write [7:0] 00000000 0x14 Read/Write [7:0] 00000000 0x15 Read [7] 0******* ...
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Hex Read/Write Default Address or Read Only Bits Value [0] *******0 0x17 Read [3:0] ****0000 0x18 Read [7:0] 00000000 0x19 Read/Write [7:0] 00001000 0x1A Read/Write [7:0] 00010100 0x1B Read/Write [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [1] ...
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AD9396 Hex Read/Write Default Address or Read Only Bits Value 0x21 Read/Write [7] 1******* [6] *1****** [5] **0***** [4] ***0**** [3] **** 1*** [2] **** *1** 0x22 Read/Write [7:0] 4 0x23 Read/Write [7:0] 32 0x24 Read/Write [7] 1******* [6] *1****** ...
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Hex Read/Write Default Address or Read Only Bits Value [3:2] ****00** [1] ******1* [0] *******0 0x26 Read/Write [7] 0******* [6] *0****** [3] ****1*** [2:1] *****00* [0] *******0 0x27 Read/Write [7] 1******* [6] *0****** [4] ***0**** [3] ****0*** [2:0] *****000 0x28 ...
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AD9396 Hex Read/Write Default Address or Read Only Bits Value 0x30 Read [6] *0****** [5] **0***** [4] ***0**** 0x31 Read/Write [7:4] 1001**** [3:0] ****0110 0x32 Read/Write [7] 0******* [6] *0****** [5:0] **001101 0x33 Read/Write [7] 1******* [6] *0****** [5:0] **010101 ...
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Hex Read/Write Default Address or Read Only Bits Value 0x39 Read/Write [4:0] ***00000 0x3A Read/Write [7:0] 00000000 0x3B Read/Write [4:0] ***11001 0x3C Read/Write [7:0] 11010111 0x3D Read/Write [4:0] ***11100 0x3E Read/Write [7:0] 01010100 0x3F Read/Write [4:0] ***01000 0x40 Read/Write [7:0] ...
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AD9396 Hex Read/Write Default Address or Read Only Bits Value 0x4B Read/Write [4:0] ***11000 0x4C Read/Write [7:0] 10111101 0x50 Read/Write [7:0] 00100000 0x56 Read/Write [7:0] 00001111 0x59 Read/Write [6] [5] [4] [0] Register Name Description CSC_Coeff_C4 MSB, Register 0x4C. MSB ...
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SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit value that reflects the current chip revision. PLL DIVIDER CONTROL 0x01—Bits[7:0] PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio PLLDIV. The ...
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AD9396 INPUT GAIN 0x05—Bits[7:0] Red Channel Gain These bits control the programmable gain amplifier (PGA) of the red channel. The AD9396 can accommodate input signals with a full-scale range of between 0.5 V p-p and 1.0 V p-p. Setting the ...
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SOG Comparator Threshold Exit The exit level for the SOG slicer. Must be > the enter level (Register 0x0F). The power-up default is 0x10. 0x11—Bit[7] HSYNC Source 0 = HSYNC SOG. The power-up default is 0. These ...
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AD9396 0x15—Bit[5] VSYNC0 Detection Bit Indicates if VSYNC0 is active. This bit is used to indicate when activity is detected on the VSYNC0 input pin. If VSYNC is held high or low, activity is not detected. The sync processing block ...
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Clamp Disable 0 = internal clamp enabled internal clamp disabled. The power-up default is 0. 0x1B —Bits[2:1] Programmable Bandwidth x0 = low bandwidth high bandwidth. The power-up default is 1. 0x1B—Bit[0] Hold Auto-Offset 0 = ...
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AD9396 If the VSYNC occurs near the HSYNC edge, this guarantees that the VSYNC edge follows the HSYNC edge. This performs filtering also in that it requires a minimum of 64 lines between VSYNCs. The VSYNC filter cleans up extraneous ...
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Output Drive Strength These two bits select the drive strength for all the high speed digital outputs (except VSOUT, A0, and the O/E Field). Higher drive strength results in faster rise times/fall times and makes it easier to capture ...
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AD9396 BT656 GENERATION 0x27—Bit[4] BT656 Enable This bit enables the output to be BT656-compatible with defined start of active video (SAV) and end of active video (EAV) controls to be inserted. These require specification of the number of active lines, ...
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Macrovision Settings Override This defines whether preset values are used for the MV line counts and pulse widths or the values stored use hard-coded settings for line counts and pulse widths use ...
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AD9396 0x44—Bits[7:0] CSC B4 LSBs 0x45—Bits[4:0] CSC C1 MSBs The default value for the 13-bit C1 is 0x0000. 0x46—Bits[7:0 CSC C1 LSBs 0x47—Bits[4:0 CSC C2 MSBs The default value for the 13-bit C2 is 0x0800. 0x48—Bits[7:0] CSC C2 LSBs 0x49—Bits[4:0] ...
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SERIAL CONTROL PORT A 2-wire serial interface control is provided in the AD9396 two AD9396 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface comprises a ...
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AD9396 Serial Interface Read/Write Examples Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control ...
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PCB LAYOUT RECOMMENDATIONS The AD9396 is a high precision, high speed analog device. To achieve the maximum performance from the part impor- tant to have a well laid-out board. The following is a guide for designing a board ...
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AD9396 OUTPUTS (BOTH DATA AND CLOCKS) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which require more current that causes more internal digital noise. Shorter traces reduce the possibility of ...
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COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 22. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9396) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x2C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E Value ...
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AD9396 Table 26. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x28 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Max Speeds (MHz) Model Analog 1 AD9396KSTZ-100 100 1 AD9396KSTZ-150 150 AD9396/PCB Pb-free part. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 0.20 0.09 7° 3.5° 25 0° ...
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AD9396 NOTES Rev Page ...
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NOTES Rev Page AD9396 ...
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AD9396 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...