M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 42
M58WR032KU70ZA6U
Manufacturer Part Number
M58WR032KU70ZA6U
Description
NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
Manufacturer
NUMONYX
Datasheet
1.M58WR032KU70ZA6U.pdf
(123 pages)
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Configuration Register
8
8.1
8.2
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Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Read Modes section for details on read operations.
The Configuration Register is set through the Command Interface. After a Reset or Power-
Up the device is configured for asynchronous read (CR15 = 1). The Configuration Register
bits are described in
X latency and the Read operation. Refer to Figures
burst configurations.
Read Select bit (CR15)
The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus
Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous;
when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst
Read is supported in both parameter and main blocks and can be performed across banks.
On reset or power-up the Read Select bit is set to’1’ for asynchronous access.
Bus Invert Configuration (CR14)
The Bus Invert Configuration bit is used to enable the BINV functionality. When the
functionality is enabled, if the BINV pin operates as an input pin (during write bus
operations), the BINV signal must always be driven; if it operates as an output pin (during
read bus operations), the functionality is valid only during synchronous read operations.
Table 12
They specify the selection of the burst length, burst type, burst
7
and
8
for examples of synchronous
M58WRxxxKU, M58WRxxxKL
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