EX256-TQG100 Actel, EX256-TQG100 Datasheet - Page 27

• Manufacturer Part Number: EX256-TQG100
• Manufacturer: Actel

Table 1-17 • eX Family Timing Characteristics
Parameter
t
t
t
t
t
d
d
d
3.3 V LVTTL Output Module Timing
t
t
t
t
t
t
t
t
d
d
d
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
ENZL
ENZLS
ENZH
ENLZ
ENHZ
DLH
DHL
DHLS
ENZL
ENZLS
ENZH
ENLZ
ENHZ
TLH
THL
THLS
TLH
THL
THLS
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
(Worst-Case Automotive Conditions, V
Description
Enable-to-Pad, Z to L
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—Low Slew
Enable-to-Pad, Z to L
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
PD
+ t
RD1
1
(V
+ t
CCI
PDn
= 3.0 V)
, t
RCO
CCA
+ t
RD1
= 2.3 V, T
+ t
v3.2
PDn
or t
J
= 125°C)
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Min.
‘Std.’ Speed
eX Automotive Family FPGAs
Max.
0.058
0.028
0.090
0.038
0.028
0.090
21.2
17.4
17.4
4.9
4.5
6.1
3.8
7.1
5.0
4.0
5.0
5.0
4.8
Units
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-23