A8514KLPTR-T Allegro Microsystems Inc, A8514KLPTR-T Datasheet - Page 14

• Manufacturer Part Number: A8514KLPTR-T
• Description: IC LED DVR WHT 4X80MA 16-ETSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A8514KLPTR-T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A8514
Sync
The A8514 can also be synchronized using an external clock
on the FSET/SYNC pin. Figure 8 shows the correspondence of
a sync signal and the FSET/SYNC pin, and figure 9 shows the
result when a sync signal is detected: the LED current does not
show any variation while the frequency changeover occurs. At
power-up if the FSET/SYNC pin is held low, the IC will not
power-up. Only when the FSET/SYNC pin is tri-stated to allow
the pin to rise, to about 1 V, or when a synchronization clock is
detected, will the A8514 try to power-up.
The basic requirement of the sync signal is 150 ns minimum on-
time and 150 ns minimum off time, as indicated by the specifica-
tions for t
for a synchronization clock into the A8514 at 2.2 MHz. Thus any
pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to
synchronize the IC.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
If during operation a sync clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor R
ing this period the IC will stop switching for a maximum period
of about 7 μs to allow the sync detection circuitry to switch over
to the externally preset switching frequency.
If the clock is held low for more than 7 μs, the A8514 will shut
down. In this shutdown mode the IC will stop switching, the
input disconnect switch is open, and the LEDs will stop sinking
current. To shutdown the IC into low power mode, the user must
disable the IC using the PWM pin, by keeping the pin low for a
period of 32,750 clock cycles. If the FSET/SYNC pin is released
at any time after 7 μs, the A8514 will proceed to soft start.
SYNC Pulse Frequency
PWSYNCON
(MHz)
0.800
0.600
2.2
2
1
and t
PWSYNCOFF
. Figure 10 shows the timing
Duty Cycle Range
33 to 66
30 to 70
15 to 85
12 to 88
9 to 91
(%)
Wide Input Voltage Range, High Efficiency
FSET
. Dur-
Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch
node; shows V
(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 μs/div.
Figure 9. Transition of the SW waveform when the SYNC pulse is
detected. The A8514 switching at 2 MHz, applied SYNC pulse at 1 MHz;
shows V
2 V/div.), and SW node (ch4, 20 V/div.), time = 5 μs/div.
Figure 10. SYNC pulse on and off time requirements.
C1
C2
C3
C4
C1
C2
C3
C4
OUT
2 MHz operation
(ch1, 20 V/div.), I
OUT
Fault Tolerant LED Driver
(ch1, 20 V/div.), I
t
PWSYNCON
150 ns
T = 454 ns
OUT
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
154 ns
FSET/SYNC
(ch2, 200 mA/div.), FSET/SYNC (ch3,
FSET/SYNC
SW node
t
SW node
t
OUT
V
V
I
I
OUT
OUT
t
OUT
OUT
PWSYNCOFF
(ch2, 200 mA/div.), FSET/SYNC
150 ns
1 MHz operation
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