A8514KLPTR-T Allegro Microsystems Inc, A8514KLPTR-T Datasheet - Page 23

• Manufacturer Part Number: A8514KLPTR-T
• Description: IC LED DVR WHT 4X80MA 16-ETSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A8514KLPTR-T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A8514
• 2X current limit
preset current limit threshold, the A8514 will shut down in less
than 3 μs regardless of user input (figure 31). This is a latched
condition. The Fault flag is also set to indicate a fault. This
feature is meant to prevent catastrophic failure in the system due
to inductor short to ground, switch pin short to ground, or output
short to ground.
Setting the current sense resistor
The typical threshold for the current sense circuit is 104 mV,
when R
resistor. The typical 1X trip point should be set at about 3 A,
which coincides with the cycle-by-cycle current limit minimum
threshold.
For example, given 3 A of input current, and the calculated maxi-
mum value of the sense resistor, R
The R
Also:
The trip point voltage is calculated as:
Input UVLO
When V
A8514 is enabled. A8514 is disabled when V
V
to avoid shutting down because of momentary glitches in the
input power supply. When V
shut down (see figure 32).
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect the capacitor C
this pin. The internal LDO can deliver no more than 2 mA of cur-
rent with a typical V
as the pull-up voltage for the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin.
Shutdown
If the PWM/EN pin is pulled low for more than t
clock cycles), the device enters shutdown mode and clears all
UVLOfall
SC
ADJ
IN
R
chosen is 0.03 Ω, a standard.
V
R
threshold for more than 50 μs. This small delay is used
ADJ
ADJ
ADJ
and V
is 0 Ω. This voltage can be trimmed by the R
= (V
= 3.0 A × 0.03 Ω = 0.090 V
= (0.104 – 0.09 V) / (20.3 μA) = 731 Ω
SENSE
If the input current level goes above 2X of the
SENSETRIP
DD
rise above the V
of about 3.5 V, enabling this pin to serve
VDD
IN
with a value of 0.1 μF or greater to
– V
falls below 4.35 V, the IC will
ADJ
SC
) / I
= 0.033 Ω.
UVLOrise
ADJ
IN
falls below the
threshold, the
PWML
Wide Input Voltage Range, High Efficiency
(32,750
ADJ
(6)
Figure 33. Shutdown using the enable function, showing the 16 ms
delay between the PWM/EN signal and when the VDD and GATE of
the disconnect switch turns off; shows GATE (ch1, 10 V/div.), I
200 mA/div.), V
ms/div.
C1
C2
C3
C4
Figure 32. Shutdown showing a falling input voltage (V
(ch1, 2 V/div.), I
(ch4, 2 V/div.), time = 5 ms/div.
C1
C2
C3
C4
Fault Tolerant LED Driver
DD
OUT
(ch3, 5 V/div.), and PWM/EN (ch4, 2 V/div.), time = 5
(ch2, 200 mA/div.), V
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
t
t
DD
(ch3, 5 V/div.), and PWM/EN
PWM/EN
PWM/EN
GATE
I
I
V
IN
V
V
OUT
OUT
DD
DD
); shows V
IN
OUT
(ch2,
IN
23