A8514KLPTR-T Allegro Microsystems Inc, A8514KLPTR-T Datasheet - Page 3

• Manufacturer Part Number: A8514KLPTR-T
• Description: IC LED DVR WHT 4X80MA 16-ETSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A8514KLPTR-T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A8514
Thermal Characteristics
Package Thermal Resistance
*Additional thermal information available on the Allegro website
Characteristic
Terminal List Table
11,12,13,14
16,17.18
Number
10
15
19
20
1
2
3
4
5
6
7
8
9
–
FSET/SYNC
PWM/EN
VSENSE
¯ F ¯ ¯ A ¯ ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
APWM
COMP
AGND
PGND
Name
GATE
LEDx
Pin-out Diagram
ISET
VDD
may require derating at maximum conditions, see application information
OVP
PAD
VIN
SW
Symbol
Output gate driver pin for external P-channel FET control.
Connect this pin to the negative sense side of the current sense resistor R
voltage is measured as V
threshold adjustment.
Input power to the A8514 as well as the positive input used for current sense resistor.
Indicates a fault condition. Connect a 100 kΩ resistor between this pin and the required logic
level voltage. The pin is an open drain type configuration that will be pulled low when a fault
occurs.
Output of the error amplifier and compensation node. Connect a series R
this pin to ground for control loop compensation.
Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the
internal I
PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also
used to enable the A8514.
Frequency/synchronization pin. A resistor R
frequency. This pin can also be used to synchronize two or more A8514s in the system. The
maximum synchronization frequency is 2.3 MHz.
Connect the R
LED signal ground.
Connect the cathodes of the LED strings to these pins.
Output of internal LDO; connect a 0.1 μF decoupling capacitor between this pin and ground.
Power ground for internal DMOS device.
Overvoltage Condition (OVP) sense; connect the R
adjust the overvoltage protection.
The drain of the internal DMOS switch of the boost converter.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad.
R
θJA
SET
Wide Input Voltage Range, High Efficiency
current.
On 2-layer PCB, 3 in.
On 4-layer PCB based on JEDEC standard
(estimated)
ISET
FSET/SYNC
PWM/EN
VSENSE
APWM
resistor between this pin and ground to set the 100% LED current.
FAULT
COMP
AGND
GATE
ISET
VIN
10
1
2
3
4
5
6
7
8
9
IN
Test Conditions*
– V
SENSE
2
. There is also a fixed current sink to allow for trip
Function
20
19
18
17
16
15
14
13
12
11
FSET
SW
OVP
PGND
PGND
PGND
VDD
LED1
LED2
LED3
LED4
Fault Tolerant LED Driver
from this pin to ground sets the switching
OVP
resistor from V
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
Value
OUT
40.0
29.0
Z
SC
-C
to this pin to
. The threshold
Z
network from
ºC/W
ºC/W
Unit
3