LFE2M20E-5FN256I Lattice, LFE2M20E-5FN256I Datasheet - Page 89

• Manufacturer Part Number: LFE2M20E-5FN256I
• Description: IC FPGA 20KLUTS 140I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
SERDES High Speed Data Transmitter (LatticeECP2M Family Only)
Table 3-7. Serial Output Timing and Levels
Table 3-8. Channel Output Jitter
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with PRBS 2
10X mode.
V
V
V
V
V
T
T
Z
R
1. All measurements are with 50 ohm impedance.
2. See technical note TN1124, LatticeECP2/M SERDES/PCS Usage Guide for actual binary settings and the min-max range.
TX-R
TX-F
TX-OI-SE
TX-DIFF-P-P-1.25
TX-DIFF-P-P-1.4
TX-DIFF-P-P-1.0
TX-DIFF-P-P-1.2
OCM
LTX-RL
Description
Symbol
Differential swing (1.25V setting)
Differential swing (1.4V setting)
Differential swing (1.0V setting)
Differential swing (1.2V setting)
Output common mode voltage
Rise time (20% to 80%)
Fall time (80% to 20%)
Output Impedance 50/75/HiZ K Ohms
(single ended)
Return loss (with package)
3.125 Gbps
3.125 Gbps
3.125 Gbps
2.5Gbps
2.5Gbps
2.5Gbps
1.25 Gbps
1.25 Gbps
1.25 Gbps
250 Mbps
250 Mbps
250 Mbps
Frequency
Description
7
-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock @
1, 2
1, 2
1, 2
Min.
1, 2
—
—
—
—
—
—
—
—
—
—
—
—
3-38
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
Frequency
—
—
—
—
—
Typ.
0.08
0.22
0.33
0.05
0.17
0.24
0.03
0.10
0.15
0.04
0.12
0.15
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Min.
—
—
—
—
—
—
—
—
—
Max.
0.12
0.38
0.43
0.11
0.30
0.39
0.11
0.18
0.29
0.17
0.13
0.29
50/75
Typ.
1.25
HiZ
1.4
1.0
1.2
0.8
70
70
9
Max.
—
—
—
—
—
—
—
—
—
1, 2
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Units
Ohms
V, p-p
V, p-p
V, p-p
V, p-p
Units
dB
ps
ps
V