LFXP20E-4F256C Lattice, LFXP20E-4F256C Datasheet - Page 364

• Manufacturer Part Number: LFXP20E-4F256C
• Description: IC FPGA 19.7KLUTS 188I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-4F256C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Therefore:
Isolating the board delays, we get:
Conclusion: To meet read set-up and hold timing, board delay for ddr_dq, ddr_clk and ddr_clk_n should be:
Write Operation
For a proper write operation, data (ddr_dq) should meet set-up (t
SDRAM with respect to ddr_dqs signal. The ddr_dqs signal is generated with respect to negative edge of
pll_nclk and data ddr_dq out is generated with respect to positive edge of pll_nclk as shown in Figure 18-3.
As a result, 1/2 clk2x (3.75ns/2) is provided as set-up and hold for ddr_dq_out with respect to dqs_out.
For maximum set-up and hold margin, the ddr_dqs and ddr_dq traces on the board should be matched.
Table 18-2. Write Operation Timing Arcs
Figure 18-3. Write Timing Diagram
Write Set-up
t
t
t
t
t
DS
DH
CDQ
CDQS
BDDS
Min. Delay of Clock to ddr_dq_in flops = t
To meet hold time at ddr_dq_in flops, Data Delay - Clock Delay > 0
t
(t
(t
(t
-0.458ns < (t
Clock Delay = t
Data Delay = t
DDR_CLK
BDD
BDD
BDD
pll_nclk (clk2x)
Symbol
ddr_dq_out
+ t
+ t
+ t
dqs_out
BDC
BDC
BDC
(min) + t
) > t
) > (1.239) ns + 0.3 + (-1.609ns) - (1.138) - (-0.75) - 0
) > -0.458 ns
BDD
Set-up time required by the DQ with respect to DQS for DDR SDRAM.
Hold time required by the DQ with respect to DQS for DDR SDRAM.
Clock-to-out timing for ddr_dq with respect to pll_nclk.
Clock-to-out timing for ddr_dqs with respect to pll_nclk.
Board delay of ddr_dqs from FPGA to DDR SDRAM pins.
CDQ
CDQS
FPGA_CLK
+ t
BDC
+ t
BDC
+ 1/2 clk2x - t
+ t
BDD
) < -0.03ns
AC
(min) + t
(min) + t
SKEW
BDD
DS
+ t
t
+ t
+ t
CDQS
FDH
BDDS
PD
FPGA_CLK
- t
- t
Description
FPGA_CLK
DDR_CLK
18-4
(min) + t
(min) - t
(min) - t
for the DDR SDRAM Controller IP Core
DS
SKEW
t
AC
) and hold (t
CDQ
SKEW
(min) - t
+ t
- t
FDH
FDH
PD
Board Timing Guidelines
> 0
DH
) time requirements of DDR
ORCA 4
0.75 ns
0.75ns
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