AT24C128C-SSHM-T Atmel, AT24C128C-SSHM-T Datasheet - Page 9

• Manufacturer Part Number: AT24C128C-SSHM-T
• Manufacturer: Atmel

Specifications of AT24C128C-SSHM-T

• Lead Free Status / Rohs Status: Compliant

8734A–SEEPR–1/11
7.
Figure 6-1.
Note:
PAGE WRITE: The 128K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see
Figure 6-2.
Note:
The lower six bits of the data word address are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64
data words are transmitted to the EEPROM, the data word address will “roll over,” and previous data will be overwritten.
The address roll over during write is from the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write select bit is representative of the operation desired. Only if the internal write cycle has completed will the
EEPROM respond with a zero, allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll over during read is from the last byte of the last memory page to the first byte of the first
page.
*
*
= Don’t-care bit
= Don’t-carebit
Byte Write
Page Write
Figure
6-2).
Atmel AT24C128C
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