PPC440GX-3NF667C Applied Micro Circuits Corporation, PPC440GX-3NF667C Datasheet - Page 89

• Manufacturer Part Number: PPC440GX-3NF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.20 – June 9, 2009
Initialization
The PPC440GX provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GX start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) (recommended value is 3kΩ to
3.3V) or pull-down (logical 0) (recommended value is 1 kΩ to GND) resistors to select the desired default
conditions. They are used for strap functions only during reset. Following reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of SysReset, if the bootstrap controller is enabled, the PPC440GX
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2, and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440GX Embedded
Processor User’s Manual.
AMCC
Strapping Pin Assignments
Serial device is disabled. Each of the four options (A–
D) is a combination of boot source, boot-source width,
and clock frequency specifications. Refer to the IIC
Bootstrap Controller chapter in the PPC440GX
Embedded Processor User’s Manual for details.
Serial device is enabled. The option being
selected is the IIC0 slave address that will
respond with strapping data.
Data Sheet
Function
440GX – Power PC 440GX Embedded Processor
Option
0x54
0x50
A
B
C
D
(UART0_DCD)
V24
0
0
0
1
1
1
Ball Strapping
(UART0_DSR)
V02
0
x
1
0
0
1
(GMC1TxEr)
L07
0
1
0
0
1
1
89