IDTQS5LV919-100Q IDT, Integrated Device Technology Inc, IDTQS5LV919-100Q Datasheet - Page 3

• Manufacturer Part Number: IDTQS5LV919-100Q
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDTQS5LV919-100Q

• Number Of Elements: 1
• Pll Input Freq (min): 2.5MHz
• Pll Input Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: QSOP
• Output Frequency Range: 5 to 100MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEEDBACK
F
FREQ_SEL
F
F
Symbol
F
Pin Name
REF_SEL
F
MAX_2XQ
F
MAX_Q/2
MIN_2XQ
OE/RST
PLL_EN
MIN_Q/2
SYNC
SYNC
MAX_Q
MIN_Q
Q
AGND
LOCK
AV
GND
2xQ
Q/2
V
0
PE
Q
DD
-Q
DD
5
4
0
1
A
= –40°C to +85°C, AV
Description
Max Frequency, 2xQ
Max Frequency, Q
Max Frequency, Q/2
Min Frequency, 2xQ
Min Frequency, Q
Min Frequency, Q/2
I/O
—
—
—
—
O
O
O
O
O
I
I
I
I
I
I
I
I
Reference clock select. When 1, selects SYNC
Description
Reference clock input
Reference clock input
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different
output frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be
synchronized to the inputs.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When
1, outputs are enabled.
PLL enable. Enables and disables the PLL. Useful for testing purposes.
When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with
the negative edge of SYNC.
Power supply for output buffers.
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
Ground supply for phase lock loop and other internal circuitries.
0
0
- Q
DD
- Q
4
/ V
4
, Q
, Q
DD
5
5
= 3.3V ± 0.3V
13.75
– 55
27.5
55
20
10
5
– 70
17.5
70
35
20
10
5
1
. When 0, selects SYNC
3
– 100
100
50
25
20
10
5
0
.
– 133
33.25
INDUSTRIAL TEMPERATURE RANGE
66.5
133
20
10
5
– 160
160
80
40
20
10
5
Units
MHz
MHz
MHz
MHz
MHz
MHz