IDT7164S15TP IDT, Integrated Device Technology Inc, IDT7164S15TP Datasheet - Page 8

• Manufacturer Part Number: IDT7164S15TP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7164S15TP

• Density: 64Kb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 13b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 110mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 8K
• Lead Free Status / Rohs Status: Not Compliant

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS
2. t
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
6. Transition is measured ±200mV from steady state.
ADDRESS
ADDRESS
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
DATA
turn off and data to be placed on the bus for the required t
write pulse width is as short as the specified t
DATA
WR1, 2
DATA
CS
CS
CS
CS
OUT
WE
WE
is measured from the earlier of CS
IN
IN
2
1
1
2
1
LOW transition or CS
(3)
2
HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
1
t
or WE going HIGH or CS
AS
t
WP
WHZ
t
.
AS
(6)
DW
1
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
and a HIGH CS
t
AW
2
going LOW to the end of the write cycle.
(4)
t
AW
t
WC
t
WC
2
8
.
t
WP
(5)
Military, Commercial, and Industrial Temperature Ranges
t
DW
t
CW
DATA VALID
t
DW
DATA VALID
t
WR1 (2)
t
DH1,2
t
WP
OW
t
DH1,2
or (t
(6)
WHZ
t
t
WR2 (2)
WR1 (2)
+t
DW
) to allow the I/O drivers to
(1)
(1,5)
2967 drw 09
2967 drw 08