UPD431000AGW-70LL Renesas Electronics America, UPD431000AGW-70LL Datasheet
UPD431000AGW-70LL
Specifications of UPD431000AGW-70LL
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UPD431000AGW-70LL Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Description μ The PD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. μ The PD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. ...
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Ordering Information Part number Package μ PD431000AGW-70L 32-pin PLASTIC SOP μ PD431000AGW-85L (13.34 mm (525)) μ PD431000AGW-70LL μ PD431000AGW-85LL μ PD431000AGW-A10 μ PD431000AGW-B12 μ PD431000AGW-B15 μ PD431000AGZ-70LL-KJH 32-pin PLASTIC TSOP(I) μ PD431000AGZ-B15-KJH (8x20) (Normal bent) μ PD431000AGZ-70LL-KKH 32-pin PLASTIC TSOP(I) ...
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Part number Package μ PD431000AGW-70L-A 32-pin PLASTIC SOP μ PD431000AGW-85L-A (13.34 mm (525)) μ PD431000AGW-70LL-A μ PD431000AGW-85LL-A μ PD431000AGW-A10-A μ PD431000AGW-B12-A μ PD431000AGW-B15-A μ PD431000AGZ-70LL-KJH-A 32-pin PLASTIC TSOP(I) μ PD431000AGZ-B10-KJH-A (8x20) (Normal bent) μ PD431000AGZ-70LL-KKH-A 32-pin PLASTIC TSOP(I) (8x20) (Reverse ...
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Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin PLASTIC SOP (13.34 mm (525)) NC A16 A14 A12 I/O1 I/O2 I/O3 GND Remark Refer to Package Drawings for the 1-pin index ...
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PLASTIC TSOP(I) (8x20) (Normal bent) μ [ PD431000AGZ-xxLL-KJH] μ [ PD431000AGZ-Bxx-KJH] μ [ PD431000AGZ-xxLL-KJH-A] μ [ PD431000AGZ-Bxx-KJH-A] A11 A13 4 /WE 5 CE2 6 A15 A16 10 A14 ...
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PLASTIC TSOP(I) (8x13.4) (Normal bent) A11 A13 4 /WE 5 CE2 6 A15 A16 10 A14 11 A12 32-pin ...
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Block Diagram V CC GND A0 Address buffer A16 I/O1 I/O8 /CE1 CE2 /OE /WE Truth Table /CE1 CE2 /OE × × H × L × × Remark × ...
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Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Note –3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause ...
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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition Input leakage current I/O leakage I/O CC current /CE1 ...
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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Input leakage current I/O leakage current I Operating ...
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AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions μ μ [ PD431000A-70L, PD431000A-85L, Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V 0.8 V Output Waveform 1.5 V Output Load AC characteristics should ...
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Read Cycle (1/2) Parameter Symbol Read cycle time t RC Address access time t AA /CE1 access time t CO1 CE2 access time t CO2 /OE to output valid t OE Output hold from address change t OH /CE1 to ...
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Read Cycle Timing Chart Address (Input) /CE1 (Input) CE2 (Input) /OE (Input) I/O (Output) Remark In read cycle, /WE should be fixed to high level CO1 t LZ1 t CO2 t LZ2 ...
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Write Cycle (1/2) Parameter Symbol ` Write cycle time t WC /CE1 to end of write t CW1 CE2 to end of write t CW2 Address valid to end of write t AW Address setup time t AS Write pulse ...
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Write Cycle Timing Chart 1 (/WE Controlled) Address (Input) /CE1 (Input) CE2 (Input /WE (Input) I/O (Input / Output) Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. ...
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Write Cycle Timing Chart 2 (/CE1 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated not input data ...
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Write Cycle Timing Chart 3 (CE2 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated not input data ...
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Low V Data Retention Characteristics (T CC Parameter Symbol Test Condition Data retention V /CE1 ≥ V − 0.2 V, CCDR1 CC supply voltage CE2 ≥ V − 0 CE2 ≤ 0 CCDR2 Data retention I ...
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Data Retention Timing Chart (1) /CE1 Controlled t CDR V CC Note 4.5 V /CE1 V (MIN (MIN.) CCDR V (MAX.) IL GND Note A version : 3 version : 2.7 V Remark On the data ...
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Package Drawings 32-PIN PLASTIC SOP (13.34 mm (525 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC TSOP(I) (8x20 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ...
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PLASTIC TSOP(I) (8x20 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX ...
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PLASTIC TSOP(I) (8x13. NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm ...
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PLASTIC TSOP(I) (8x13. NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm ...
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Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the Types of Surface Mount Device μ PD431000AGW-xxL : 32-pin PLASTIC SOP (13.34 mm (525)) μ PD431000AGW-xxLL : 32-pin PLASTIC SOP (13.34 mm (525)) μ PD431000AGW-Axx : ...
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Revision History Edition/ Page Date This Previous edition edition 14th edition/ through through Modification Nov. 2009 26 Type of Description revision Ordering Information revised. Data Sheet M11657EJEV0DS μ PD431000A ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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The information in this document is current as of November, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for the most up-to-date specifications of ...