LH28F800SGN-L10 Sharp Electronics, LH28F800SGN-L10 Datasheet
LH28F800SGN-L10
Specifications of LH28F800SGN-L10
Available stocks
Related parts for LH28F800SGN-L10
LH28F800SGN-L10 Summary of contents
Page 1
... SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SG-L offers three levels of protection : absolute protection with V ...
Page 2
COMPARISON TABLE VERSIONS OPERATING TEMPERATURE LH28F800SG +70˚C (FOR SOP) 1 LH28F800SG +70˚C (FOR TSOP, CSP) 1 LH28F800SGH-L – +85˚C (FOR TSOP, CSP) 1 Refer to the datasheet of LH28F800SG-L/SGH-L (FOR TSOP, CSP). PIN CONNECTIONS ...
Page 3
BLOCK DIAGRAMS Y DECODER INPUT BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 16 32 k-WORD BLOCKS - 3 - LH28F800SG-L ...
Page 4
... DEVICE POWER SUPPLY : Internal detection configures the device for 2 operation. To switch from one voltage to another, ramp V ramp V V SUPPLY CC attempts to the flash memory are inhibited. Device operations at invalid V (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GND SUPPLY GROUND : Do not float any ground pins. ...
Page 5
... Product Overview The LH28F800SG high-performance 8 M-bit SmartVoltage flash memory organized as 512 k- word of 16 bits. The 512 k-word of data is arranged in sixteen 32 k-word blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Fig ...
Page 6
The selected block can be locked or unlocked individually by the combination of sixteen block lock bits and the RP#. Block erase or word write must not be carried out by setting block lock bits and RP ...
Page 7
... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage ...
Page 8
... RP# goes to logic-high (V command can be written with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash ), the device memory. Automated flash memories provide status IH -DQ are information when accessed during block erase, ...
Page 9
Read Identifier Codes The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the permanent lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU ...
Page 10
MODE NOTE Read Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier Codes 8 Write NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS". ≤ V When V , ...
Page 11
BUS CYCLES COMMAND REQ Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume Set Block Lock-Bit Set Permanent Lock-Bit Clear Block Lock-Bits ...
Page 12
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 13
Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status ...
Page 14
... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
Page 15
Fig. 7). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status ...
Page 16
PERMANENT BLOCK OPERATION LOCK-BIT LOCK-BIT X 0 Block Erase Word Write 1 Set Block 0 X Lock-Bit 1 Set Permanent X X Lock-Bit Clear Block 0 X Lock-Bits 1 WSMS ESS ECLBS SR.7 = ...
Page 17
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 18
Start Write 40H, Address Write Word Data and Address Read Status Register Suspend Word No Write Loop 0 Yes Suspend SR.7 = Word Write 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 19
Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Word Write or Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
Page 20
Start Write B0H Read Status Register 0 SR Word Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write ...
Page 21
Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
Page 22
Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
Page 23
... GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V trace. The V pin supplies the memory cell current PP for word writing and block erasing ...
Page 24
... IL When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility or CE# PP increases usable battery life because data is retained when system power is removed. ...
Page 25
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature During Read, Block Erase, Word Write and Lock-Bit Configuration ...... 0 to +70°C Temperature under Bias ............. –10 to +80°C Storage Temperature ....................... – +125°C Voltage On Any Pin ...
Page 26
AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and ...
Page 27
DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power-Down CC I CCD Current I V Read Current CCR CC V Word Write ...
Page 28
DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL Output High Voltage V OH1 (TTL) Output High Voltage V OH2 (CMOS) V Lockout Voltage during PP V PPLK ...
Page 29
AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
Page 30
AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High ...
Page 31
Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) ( ...
Page 32
AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# ...
Page 33
AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to WE# t PHWL Going Low t CE# Setup to WE# ...
Page 34
V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High DATA (D/Q) t PHWL V IL ...
Page 35
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS • 2 +70˚ VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# ...
Page 36
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to CE# t PHEL Going Low t WE# Setup to CE# ...
Page 37
V IH ADDRESSES ( AVAV V IH WE# ( WLEL V IH OE# ( CE# ( High DATA (D/Q) t ...
Page 38
RESET OPERATIONS V OH RY/BY# ( RP# ( RY/BY# ( RP# ( 2.7 V/3.3 V RP# (P) V ...
Page 39
BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE • 2 +70˚ SYMBOL PARAMETER NOTE t WHQV1 Word Write Time t EHQV1 Block Write Time t WHQV2 Block Erase ...
Page 40
BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.) • 5.0±0.25 V, 5.0±0 SYMBOL PARAMETER t WHQV1 Word Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t ...
Page 41
... S = Symmetrical Block Power Supply Type G = SmartVoltage Technology Operating Temperature = OPTION ORDER CODE 1.35 V I/O Levels 1 LH28F800SGN-L70 2 LH28F800SGN-L10 Access Speed (ns (5.0 0.25 V (5.0 0.5 V 100 ns (5.0 0.5 V), 100 ns (3.3 0.3 V), Package N = 44-pin SOP (SOP044-P-0600) VALID OPERATIONAL COMBINATIONS = 2 3.3±0 load load, 1 ...
Page 42
SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...