LH28F008SCT-T9 Sharp Electronics, LH28F008SCT-T9 Datasheet - Page 10

• Manufacturer Part Number: LH28F008SCT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-T9

• Lead Free Status / Rohs Status: Compliant

2 PRINCIPLES OF OPERATION
The LH28F008SCT-T9 SmartVoltage Flash memory
includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with
RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
byte writing, and lock-bit configuration. All functions
associated with altering memory contents−block
erase, byte write, Lock-bit configuration, status, and
identifier codes−are accessed via the CUI and
verified through the status register.
Commands
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, or outputs
status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates. After successful completion, reads are
again possible via the Read Array command. Block
erase suspend allows system software to suspend a
block erase to read or write data from any other
block. Byte write suspend allows system software to
suspend a byte write to read data from any other
flash memory array location.
PP
are
enables successful block erasure,
written
using
PP
voltage. High
standard
LHF08CT9
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to V
accommodates
encourages optimization of the processor-memory
interface.
When V
altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V
functions are disabled when V
lockout voltage V
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.
DFFFF
FFFFF
EFFFF
CFFFF
BFFFF
AFFFF
9FFFF
8FFFF
7FFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
E0000
D0000
C0000
B0000
A0000
F0000
90000
80000
70000
60000
50000
40000
30000
20000
10000
00000
PP
≤V
Figure 3. Memory Map
PPLK
LKO
either
, memory contents cannot be
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
or when RP# is at V
design
PPH1/2/3
CC
PP
is below the write
practice
power supply
. The device
PP
. All write
15
14
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10
9
8
7
6
5
4
3
2
1
0
Rev. 1.3
IL
. The
and
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