LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet
LH28F008SCT-V12
Specifications of LH28F008SCT-V12
Related parts for LH28F008SCT-V12
LH28F008SCT-V12 Summary of contents
Page 1
... Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SC-V/SCH-V offer protection : absolute protection with V selective hardware block locking, or flexible software block locking ...
Page 2
PIN CONNECTIONS 40-PIN TSOP (Type CE RP# 12 ...
Page 3
BLOCK DIAGRAM Y DECODER INPUT BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 16 64 k-BYTE BLOCKS - 3 - LH28F008SC-V/SCH-V ...
Page 4
... HH ≤ RP# ≤ V produce spurious results and should not be attempted. HH (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results PP ≤ LH28F008SC-V/SCH-V enables setting of the HH ≤ memory PP PPLK , all write attempts to the flash memory LKO voltage (see Section 6.2.3 "DC CC ...
Page 5
... To take advantage of Smart 5 technology, allow V connection 1.2 Product Overview The LH28F008SC-V/SCH-V are high-performance 8 M-bit Smart 5 flash memories organized byte of 8 bits. The 1 M-byte of data is arranged in sixteen 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Fig.1. Smart 5 technology provides a choice of V ...
Page 6
... Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates ...
Page 7
... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage ...
Page 8
... V . Fig with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash ), the device memory. Automated flash memories provide status IH -DQ are information when accessed during block erase, byte ...
Page 9
Read Identifier Codes Operation The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system ...
Page 10
MODE NOTE Read Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier Codes 8 Write NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS". ≤ V When V , ...
Page 11
BUS CYCLES COMMAND REQ Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Byte Write Block Erase and Byte Write Suspend Block Erase and Byte Write Resume Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits ...
Page 12
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 13
Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status ...
Page 14
... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
Page 15
When the set lock-bit operation is complete, status register bit SR.4 should be checked error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. ...
Page 16
MASTER BLOCK OPERATION LOCK-BIT LOCK-BIT 0 Block Erase X or Byte Write Set Block Lock-Bit 1 X Set Master X X Lock-Bit 0 X Clear Block Lock-Bits 1 X WSMS ESS ECLBS SR.7 = ...
Page 17
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 18
Start Write 40H, Address Write Byte Data and Address Read Status Register Suspend Byte No Write Loop 0 Suspend SR.7 = Byte Write Yes 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 19
Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Byte Write or Byte Write? Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
Page 20
Start Write B0H Read Status Register 0 SR Byte Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Byte Write Resumed Array Data Fig. 6 Byte Write ...
Page 21
Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
Page 22
Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
Page 23
... GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V trace. The V pin supplies the memory cell current PP for byte writing and block erasing ...
Page 24
... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during or CE# PP system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. . LKO ...
Page 25
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature • LH28F008SC-V During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F008SCH-V During Read, Block Erase, Byte Write and ...
Page 26
CAPACITANCE SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 0.0 AC test inputs are driven at 3.0 V for a Logic ...
Page 27
DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power- LH28F008SC CCD Down Current LH28F008SCH Read Current CCR Byte ...
Page 28
DC CHARACTERISTICS (contd.) SYMBOL PARAMETER Input Low Voltage Input High Voltage IH V Output Low Voltage OL Output High Voltage V OH1 (TTL) Output High Voltage V OH2 (CMOS) V Lockout Voltage during PP V PPLK ...
Page 29
AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 5.0±0.25 V, 5.0±0 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to ...
Page 30
Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) ( ...
Page 31
AC CHARACTERISTICS - WRITE OPERATION V = 5.0±0.25 V, 5.0±0 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to WE# t PHWL Going Low t CE# Setup to WE# Going Low ...
Page 32
V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High DATA (D/Q) t PHWL V IL ...
Page 33
ALTERNATIVE CE#-CONTROLLED WRITES • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to CE# t PHEL Going Low t WE# Setup to CE# Going Low WLEL t ...
Page 34
V IH ADDRESSES ( AVAV V IH WE# ( WLEL V IH OE# ( CE# ( High DATA (D/Q) t ...
Page 35
RESET OPERATIONS V OH RY/BY# ( RP# ( RY/BY# ( RP# ( RP# ( Fig. ...
Page 36
BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE • 5.0±0.25 V, 5.0±0 SYMBOL PARAMETER t WHQV1 Byte Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t WHQV3 ...
Page 37
... ORDERING INFORMATION Product line designator for all SHARP Flash products ( Device Density 008 = 8 M-bit Architecture S = Symmetrical Block Power Supply Type C = Smart 5 Technology Operating Temperature Blank = –25 to +85 C OPTION ORDER CODE 1 LH28F008SCXX-V85 2 LH28F008SCXX-V12 LH28F008SC-V/SCH-V Access Speed (ns (5.0 0.25 V (5.0 0.5 V 120 ns (5 ...
Page 38
TSOP (TSOP040-P-1020 0.3 20.0 0.2 18.4 0.3 19.0 PACKAGING Package base plane ...
Page 39
SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...
Page 40
CSP (FBGA048-P-0608) B 0.1 S TYP. 0.8 TYP. 0 0.1 S TYP. 0 0.2 8 TYP. 1.2 0.03 0. PACKAGING Land ...