LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet - Page 9

• Manufacturer Part Number: LH28F008SCT-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Fig. 2). Using the
manufacture and device codes, the system CPU
can automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
Fig. 2 Device Identifier Code Memory Map
FFFFF
F0004
F0003
F0002
F0001
F0000
1FFFF
10004
10003
10002
10001
10000
0FFFF
00004
00003
00002
00001
00000
Block 15 Lock Configuration Code
Block 1 Lock Configuration Code
Block 0 Lock Configuration Code
Master Lock Configuration Code
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
(Blocks 2 through 14)
Manufacture Code
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Device Code
Block 15
Block 1
Block 0
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3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require
the command and address within the device
(Master Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 13 and
Fig. 14 illustrate WE# and CE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the V
from the status register, identifier codes, or blocks
are enabled. Placing V
successful block erase, byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
PP
= V
PPH1/2
PP
, the CUI additionally controls block
voltage ≤ V
LH28F008SC-V/SCH-V
PPH1/2
PPLK
, read operations
on V
PP
enables