LH28F160S5HT-L10 Sharp Electronics, LH28F160S5HT-L10 Datasheet - Page 34

• Manufacturer Part Number: LH28F160S5HT-L10
• Manufacturer: Sharp Electronics

Specifications of LH28F160S5HT-L10

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

sharp
5.5 V
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
V
outside of a valid V
error is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to V
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V
clear the status register.
The CUI latches commands issued by system
software and is not altered by V
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
V
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V
transitions down to V
read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration during
power transitions. Upon power-up, the device is
indifferent as to which power supply (V
PP
CC
transitions below V
falls outside of a valid V
CC
, V
PP
, RP# Transitions
CC1/2
PPLK
LKO
, the CUI must be placed in
range, or RP#=V
.
PPH1
PP
or CE# transitions
range, V
IL
during block
PP
IL
or V
CC
. If V
falls
CC
LHF16KA9
PP
PP
IL
)
powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either to V
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=V
5.7 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
In
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to V
standby or sleep modes. If access is again needed,
the devices can be read following the t
t
raised to V
and Write Operations and Figures 17, 18, 19, 20 for
more information.
PHWL
addition,
wake-up cycles required after RP# is first
IH
CC
IL
. See AC Characteristics Read Only
regardless of its control inputs state.
deep
voltages above V
power-down
IH
LKO
will inhibit writes.
mode
when V
PHQV
Rev. 2.0
ensures
PP
and
31
is
IL