LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet
LH28F160BJHE-BTL70
Specifications of LH28F160BJHE-BTL70
Related parts for LH28F160BJHE-BTL70
LH28F160BJHE-BTL70 Summary of contents
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... P P RELIMINARY RODUCT LH28F160BJHE-BTL70 16M (1M ×16/ PECIFICATIONS ® Flash Memory (Model No.: LHF16J07) Spec No.: FM996003 Issue Date: June 22, 1999 Integrated Circuits Group ...
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SHARP l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered ...
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SHARP ............................................................ 3 1 INTRODUCTION.. 1.1 Features ........................................................................ 1.2 Product Overview.. ...................................................... .3 1.3 Product Description ...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization ................................................. 4 2 PRINCIPLES OF OPERATION.. ..................................... .7 2.1 Data Protection.. .......................................................... .8 ........................................................... ...
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... For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160BJHE-BTL70 offers four levels of protection: absolute protection with V,--wIV,,,,, hardware block locking or flexible software block locking. These alternatives give designers ultimate control of their code security needs ...
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... Section 1 provides a flash overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of LH28F160BJHE-BTL70 Flash memory are: *Single low voltage operation ~LOW power consumption *EnhancedSuspend Capabilities *Boot Block Architecture Please note following: l VCCWLK has been lowered to l.OV to support 2.7V- 3 ...
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... For example, “10111100” requires “11111110” programming. LHFl6507 1.3 Product Description supply 1.3.1 Package Pinout LH28F160BJHE-BTL70 available in 48-lead TSOP package (see Figure 2). 1.3.2 Block Organization the I,, CMOS This product architecture providing system memory integration. Each power erase block can be erased independently of the others up to 100,000 times ...
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SHARP Al5 A14 Al3 Al? All 40 A9 ‘%J A19 NC WE# RF% vccw Wp# RYiBY# AM A17 LHF16507 Figure 1. Block Diagram 4%LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW Figure 2. TSOP ...
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... Vccw may be connected to 12VkO.6V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With Vc,+V,,O, SUPPLY the flash memory are inhibited. Device operations at invalid V,, voltage (see 6.2.3 DC “cc Characteristics) produce spurious results and should not be attempted. SUPPLY GROUND: Do not float any ground pins ...
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... This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend ...
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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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SHARI= 3.5 Read Identifier Codes The read identifier codes operation manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can ...
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SHARP JOTES: . Refer to DC Characteristics. When Vccw5V,,,,, ,. X can VI, for control pins and addresses, and V,-,,, VCCWLK voltages. . RY/BY when the WSM is executing internal block erase, full chip erase, ...
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SHARI= 2 Set Block Lock-Bit 2 Clear Block Lock-Bits 2 Set Permanent Lock-Bit NOTES: 1. BUS operations are defined in Table 2.1 and Table 2.2. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. BA=Address within ...
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SHARP 4.1 Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing command. The device remains enabled for reads until another command is ...
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SHARP 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. sequence requires appropriate sequencing and an address within ...
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... Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After ...
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SHARP 4.10 Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations ...
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... SHARI= 4.12 Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable blocks are locked when WP#=V,; program or erase operation to a locked block will result in ...
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SHARI= WSMS 1 BESS ( ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed ...
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SHARI= Write 70H Write ?OH Write DOH. Block Address Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Block Erase Error Block Erase Successful Figure 5. Automated Block Erase Flowchart LHFl6507 Check SR.7 Slandby I=WSM Ready O=WSM ...
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SHARI= FL’LL STATUS CHECK PROCEDURE Read Stalus Reglater Dat@ee Above) Command Sequence Figure 6. Automated Full Chip Erase Flowchart LHF16507 Status Regrster Read Check SR.7 Standby l=WSM O=WSM Full chip Erase Dam=3OH Write setup Ad&X Data=DOH Full chip Erase Write ...
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SHARP Write 40H or IOH Status Register Suspend Word/Byte FULL STATUS CHECK PROCEDURE Read Status Regster Data(See Above) Device Protect &or Word/Byte Write Successful Figure 7. Automated Word/Byte Write Flowchart LIP.1 6507 BUS Command operation Dam=70H Write AddrzX Stau Register ...
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SHARP Wrlre BOH Status Register Write DOH k&j &i Figure 8. Block Erase Suspend/Resume Flowchart LHFl6507 write FFH Rev. 1.2 ...
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SHARI= SWt Write BOH Figure 9. Word/Byte Write Suspend/Resume Flowchart LHF16507 BUS Command Operario I Data=BOH WordlBp Write Write Suspend Addr=X Data=FRt Read Array Write Addt=X Data=DOH WordByte Write Write Resume Ad&X 22 Rev. 1.2 ...
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SHARI= Write 70H I Read Status Writs 6oH WriteOIWFIH, Block/Device Address Check if Desired FULL STATUS CHECK PROCEDURE Device Rotect Error Set Lock-Btt Successful Figure 10. Set Block and Permanent Lock-Bit Flowchart LHFl6507 BUS Command *ratioo I Dma=TOH Read Status ...
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SHARP r FULL STATUS CHECK PROCEDURE Read Status Register at&See Above) Device Raect Error Command Sequence Clear Block Lock-Bits Clear Block Lock-Bits Successful LHFl6507 Read Status Write Rf!giSter I I Read Standby Clear Block W&e Lock-Bits Setup Clear Block Write ...
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... PC board trace inductance. 5.4 VCCW Trace on Printed Circuit Boards should also Updating flash memories that reside in the target system requires that the printed attention to the Vccw supplies the memory cell current for word/byte writing and block erasing ...
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... All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the specification. (See chapter 62.3.) 3) Data protection through RP# When the RP# is kept low during read mode, the flash memory will protecting all blocks. When the RP# is kept low during ...
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SHARP 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration . . . . . . . . . . . . . -40°C to +85”C(‘) Storage Temperature ...
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SHARI= .2.2 AC INPUT/OUTPUT TEST CONDITIONS ~Tqz=$z=+T AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0”. Input timing begins, and output timing ends, at 1.35V. Input rise and fat1 times (10% to ...
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SHARI= 5.2.3 DC CHARACTERISTICS Sym. Parameter Input Load Current IL1 Output Leakage Current IL0 V,, Standby Current kcs V,, Auto Power-Save Current ‘CCAS V,, Reset Power-Down Current ‘CCD Vcc Read Current ‘CC, 1 kcw V,, Block Erase, Full Chip Erase ...
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SHARP \ToTEs: 1. All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25”C. are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the 2. kCWS and ‘CCES ...
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SHARP 6.2.4 AC CHARACTERISTICS - READ-ONLY Parameter sym. Read Cycle Time ATIAII t rl.rx. I Address to Output Delay tAVOV NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to ...
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SHARP Device Standby Address Selection Figure 14. AC Waveform for Read Operations LHFl6507 Data Valid 32 Rev. 1.2 ...
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SHARI= Device Address Selection Standby BYTEWD Figure 15. BYTE# timing Waveform LHF16507 Data Valid Rev. 1.2 ...
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SHARI= 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(l) Parameter I Svm. I Write Cycle Time tAVAV tPHWL RP# High Recovery to WE# Going Low tELwL CE# Setup to WE# Going Low twLWH WE# Pulse Width WP#VIB Setup to WE# Going High ...
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SHARP 1 e--o-- VIH ADDRESSES(A) VU VIH CEME) VU VIH OE#(G) VU VIH VIH DATA(DIQ) VU VIH BYTE?+(F) RY/BY#(R) (SR.7) VIH RP#(P) I NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or ...
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SHARI= 62.6 ALTERNATIVE CE#-CONTROLLED WP# V,, Hold from Valid SRD, RY/BY# High Z I toVSL BYTE# Setup to CE# Going High tFVEH BYTE# Hold from CE# High fEHFV NOTES systems where CE# defines the write pulse width (within ...
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SHARI= ADDRESSES(A) DATA(D/Q) NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. ...
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SHARI= 6.2.7 RESET OPERATIONS High Z RY/BY#(R) (“1”) (SR.7) VOL (“0”) VIH RwP) VIL High Z RY/BY#(R) (“1”) (SR.7) VOL (“0”) VIH Rw? VIL (B)Reset 2.7V vcc VIL VIH RwP) VIL Figure 18. AC Waveform for Reset Operation Parameter Sym. ...
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SHARI= i.2.8 BLOCK ERASE, FULL CHIP ERASE, CONFIGURATION PERFORMANCE(3) Parameter Set Lock-Bit Time IOTES: Typical values measured at TA=+25”C and V,,=3.OV, set. Subject to change based on device characterization. Excludes system-level overhead. Sampled but not 100% tested. LHFl6507 WORD/BYTE WRITE ...
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