LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 15

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to “1”. Also, reliable block erasure can only occur when
V,,=2.7V-3.6V
this high voltage, block contents are protected against
erasure. If block erase is attempted while VccwlVccwLK,
SR.3 and SR.5 will be set to “1”. Successful block erase
requires for boot blocks that WP# is V,,
corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleard the corresponding
block lock-bit.
excepting above conditions, SR.l and SR.5 will be set to
“1”.
4.6 Full Chip Erase Command
This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (DOH).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
invisible
erase sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU can
letect full chip erase completion by analyzing the output
lata of the RY/BY# pin or status register bit SR.7.
#hen the full chip erase is complete, status register bit
JR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
ittempts corrective actions. The CUI remains in read
written, the device automatically outputs status register
data when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH).
are handled internally by the WSM (invisible
system). After the two-cycle
SHARP
to the system). After the two-cycle
by an block erase confirm.
If block erase is attempted when the
and VCCW=VCCWHIR. In the absence of
Block preconditioning, erase, and verify
block erase sequence is
This command
full chip
and the
to the
LHF16507
Reliable
Vcc=2.7V-3.6V
this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
VCCWsVCCWLK’
set to “1”. Successful word/byte write requires for boot
blocks that WP# is V,, and the corresponding block lock-
bit be cleared. In parameter and main blocks case, it must
be cleard the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR. 1 and SR.4 will be set to “1”.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 7). The CPU can detect the completion of the
word/byte
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for “1”s that do not successfully write
to “0”s. The CUI remains in read status register mode until
it receives another command.
locked, SR.1 and SR.5 will be set to “1”.
4.7 Word/Byte Write Command
Word/Byte
sequence. Word/Byte
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte
block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to “1”. Also, reliable full chip erasure can only occur
when
absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
VCCW’VCCWLK~
Successful full chip erase requires for boot blocks that
WP# is V,,
cleared. In parameter and main blocks case, it must be
cleat-d the corresponding block lock-bit. If all blocks are
status register mode until a new command is issued. It
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
V,,=2.7V-3.6V
word/byte
write event by analyzing the RY/BY# pin or
write and write verify algorithms internally.
write is executed by a two-cycle
and the corresponding block lock-bit
and VCCW=VCCWHln. In the absence of
status
SR.3 and SR.5 will
writes
register bits SR.3 and SR.4 will be
write
and VCCw=VCCWHln.
setup (standard
can
only
be set to “1”.
occur
command
Rev. 1.2
40H or
In the
when
13
be