CY7C1367A-150AC Cypress Semiconductor Corp, CY7C1367A-150AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1367A-150AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AC

• Density: 9Mb
• Access Time (max): 3.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 380mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

256K X 36 Pin Descriptions
512K X 18 Pin Descriptions
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
2F, 1G, 2G, 1H, 2H,
2M, 1N, 2N, 1P , 2P
3D, 5D, 3E, 5E, 3F,
5F, 3H, 5H, 3K, 5K,
7J, 1M, 7M, 1U, 7U
1B, 7B, 1C, 7C, 4D,
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
(c) 2D, 1D, 1E, 2E,
(d) 1K, 2K, 1L, 2L,
3J, 5J, 4L, 1R, 5R,
(a) 6P , 7P , 7N, 6N,
1A, 7A, 1F, 7F, 1J,
7R, 1T, 2T, 6T, 6U
4C, 2J, 4J, 6J, 4R
X36 PBGA Pins
3M, 5M, 3N, 5N,
X18 PBGA Pins
3P , 5P
5T, 6T
4M
2U
3U
4U
5U
4N
3G
4H
4P
5L
4K
4E
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
38, 39, 42 for TA
100, 99, 82, 81,
43 (TA Version)
X36 QFP Pins
X18 QFP Pins
40, 55, 60, 67,
35, 34, 33, 32,
80, 48, 47, 46,
92 (T Version)
45, 44, 49, 50
15, 41,65, 91
for B and T
for B and T
71, 76, 90
61, 70, 77
14, 16, 66
9, 12, 13
Version
version
version
38
39
43
42
37
36
93
94
87
88
89
98
(continued)
Name
Name
V
BWE
BWa
BWb
DQa
DQb
DQd
TMS
TDO
DQc
TCK
CLK
V
GW
V
TDI
NC
CE
A0
A1
CCQ
A
CC
SS
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Supply
Ground
Output
Output
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input/
Type
Type
Input
-
6
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set up and hold times around the rising
edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE
to occur independent of the BWE and WEn lines and must
meet the set up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around
the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the de-
vice and to gate ADSP .
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
Core power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description
Description
CC
or V
SS
.