CY7C1367A-150AC Cypress Semiconductor Corp, CY7C1367A-150AC Datasheet - Page 7

• Manufacturer Part Number: CY7C1367A-150AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AC

• Density: 9Mb
• Access Time (max): 3.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 380mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

512K X 18 Pin Descriptions
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
5F, 5G, 3H, 5H, 3K,
7J, 1M, 7M, 1U, 7U
1B, 7B, 1C, 7C, 2D,
4L, 7L, 6M, 2N, 7N,
1P , 6P , 1R, 5R, 7R,
6H, 7K, 6L, 6N, 7P
3D, 5D, 3E, 5E, 3F,
4D, 7D, 1E, 6E, 2F,
(a) 6D, 7E, 6F, 7G,
3J, 5J, 1K, 6K, 2L,
1A, 7A, 1F, 7F, 1J,
4C, 2J, 4J, 6J, 4R
X18 PBGA Pins
(not available for
1G, 6G, 2H, 7H,
5K, 3L, 3M, 5M,
3N, 5N, 3P , 5P
1T, 4T, 6U
PBGA)
4G
3R
2U
3U
4U
5U
2B
4F
4A
4B
7T
(a) 58, 59, 62, 63,
68, 69, 72, 73, 74
18, 19, 22, 23, 24
25, 28-30, 51-53,
78, 79, 80, 95, 96
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
1-3, 6, 7, 14, 16,
38, 39, 42 for TA
(b) 8, 9, 12, 13,
X18 QFP Pins
92 (for TA Ver-
40, 55, 60, 67,
56, 57, 66, 75,
15, 41,65, 91
for B and T
for B and T
71, 76, 90
61, 70, 77
sion only)
Version
version
version
97
86
83
84
85
31
64
38
39
43
42
(continued)
MODE
ADSP
ADSC
Name
V
DQa
DQb
TMS
TDO
ADV
TCK
CE
CE
V
V
TDI
OE
NC
ZZ
CCQ
CC
SS
2
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Supply
Ground
Supply
Output
Output
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Type
Input
Input
-
7
Chip Enable: This active HIGH input is used to enable the
device.
Chip Enable: This active LOW input is used to enable the de-
vice. Not available for B and T package versions.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interlinear Burst.
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input
data must meet set up and hold times around the rising edge
of CLK.
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
Core power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description
CC
or V
SS
.