CY62128DV30L-70SI Cypress Semiconductor Corp, CY62128DV30L-70SI Datasheet - Page 6

• Manufacturer Part Number: CY62128DV30L-70SI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62128DV30L-70SI

• Density: 1Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 17b
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05231 Rev. *H
Switching Waveforms
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1 (WE Controlled)
Notes:
15. Address valid prior to or coincident with CE
16. Data I/O is high-impedance if OE = V
17. If CE
18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
DATA OUT
CURRENT
ADDRESS
ADDRESS
DATA I/O
SUPPLY
V
CC
CE
CE
1
WE
CE
CE
OE
goes HIGH or CE
1
2
1
2
NOTE
2
18
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
HIGH IMPEDANCE
t
PU
(continued)
t
LZCE
IH
t
SA
.
[11, 14, 15]
t
t
[12, 16, 17, 18]
LZOE
ACE
1
transition LOW and CE
50%
t
DOE
t
AW
t
2
t
RC
SCE
t
transition HIGH.
SCE
DATA
t
t
PWE
SD
IN
DATA VALID
VALID
t
HZOE
t
HA
t
HZCE
t
HD
CY62128DV30
t
PD
50%
IMPEDANCE
HIGH
Page 6 of 11
I
I
CC
SB
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