CY7C1019CV33-10VC Cypress Semiconductor Corp, CY7C1019CV33-10VC Datasheet

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CY7C1019CV33-10VC

Manufacturer Part Number
CY7C1019CV33-10VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1019CV33-10VC

Density
1Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
80mA
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Features
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *H
Temperature Ranges
Pin and Function compatible with CY7C1019BV33
High Speed
CMOS for optimum Speed and Power
Data Retention at 2.0V
Center Power/Ground Pinout
Automatic Power Down when deselected
Easy Memory Expansion with CE and OE Options
Available in Pb-free and non Pb-free 48-Ball VFBGA, 32-Pin
TSOP II and 400-mil SOJ Package
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
t
Logic Block Diagram
AA
= 10 ns
WE
CE
OE
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
198 Champion Court
INPUT BUFFER
DECODER
128K x 8
COLUMN
ARRAY
POWER
DOWN
Functional Description
The CY7C1019CV33 is a high performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tristate drivers. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O
the address pins (A
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
0
1 Mbit (128K x 8) Static RAM
through I/O
San Jose
7
) is then written into the location specified on
0
through A
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
16
0
).
through I/O
CY7C1019CV33
Revised March 23, 2010
7
) are placed in a
408-943-2600
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CY7C1019CV33-10VC Summary of contents

Page 1

... Document #: 38-05130 Rev Mbit (128K x 8) Static RAM Functional Description The CY7C1019CV33 is a high performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tristate drivers. This device has an automatic power down feature that significantly reduces power consumption when deselected ...

Page 2

... Figure 1. 48-Ball VFBGA (Top View I I I Note 1. NC pins are not connected on the die. Document #: 38-05130 Rev. *H -10 (Industrial/ -12 (Industrial) Auto- Figure 2. 32-Pin SOJ/TSOP II (Top View I I/O I I/O I CY7C1019CV33 -15 (Industrial) Unit [ Page [+] Feedback [+] Feedback ...

Page 3

... CC – 0.3V, CC – 0.3V, CC < 0.3V Test Conditions T = 25° MHz 5.0V CC CY7C1019CV33 Ambient V CC Temperature 3.3V  10% 0°C to +70°C 3.3V  10% –40C to +85C 3.3V  10% –40C to +85C –15 (Industrial) Unit Min Max Min Max ...

Page 4

... Auto-A) Min Max Min Figure 3. 3. Transition is measured 500 mV from steady-state voltage. Figure is less than less than t , and t HZCE LZCE HZOE LZOE and t HZWE CY7C1019CV33 [4] High-Z characteristics: R 317 3.3V 10% OUTPUT 5 pF (c) -15 (Industrial) Unit Max Min Max ...

Page 5

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 38-05130 Rev. *H [11, 12] Figure 4. Read Cycle No OHA DOE DATA VALID 50 SCE t SCE PWE t SD DATA VALID CY7C1019CV33 DATA VALID [12, 13] t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB [14, 15 Page [+] Feedback [+] Feedback ...

Page 6

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05130 Rev SCE PWE t SD DATA VALID SCE PWE t SD DATA VALID Mode 7 Power Down Read Write Selected, Outputs Disabled CY7C1019CV33 [14, 15 [15 LZWE Power Standby ( Active ( Active ( Active ( Page [+] Feedback [+] Feedback ...

Page 7

... CY7C1019CV33-10ZXA 12 CY7C1019CV33-12ZXC 15 CY7C1019CV33-15VXC Package Diagrams Document #: 38-05130 Rev. *H Package Package Type Diagram 51-85095 32-pin TSOP II (Pb-Free) 51-85095 32-pin TSOP II (Pb-Free) 51-85033 32-pin 400-Mil Molded SOJ (Pb-Free) Figure 9. 32-pin (400-Mil) Molded SOJ CY7C1019CV33 Operating Range Automotive-A Commercial Commercial 51-85033 *C Page [+] Feedback [+] Feedback ...

Page 8

... Document #: 38-05130 Rev. *H Figure 10. 32-Pin TSOP II CY7C1019CV33 51-85095 *A Page [+] Feedback [+] Feedback ...

Page 9

... Document #: 38-05130 Rev. *H Figure 11. 48-Ball VFBGA ( mm) CY7C1019CV33 51-85150 *E Page [+] Feedback [+] Feedback ...

Page 10

... Document History Page Document Title: CY7C1019CV33 1 Mbit (128K x 8) Static RAM Document Number: 38-05130 Submission REV. ECN NO. Date ** 109245 12/16/01 *A 113431 04/10/02 *B 115047 08/01/02 *C 119796 10/11/02 *D 123030 12/17/02 *E 419983 See ECN *F 493543 See ECN *G 2761448 09/09/2009 *H 2897691 03/23/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...

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