CY7C1347C-200AC Cypress Semiconductor Corp, CY7C1347C-200AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1347C-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347C-200AC

• Density: 4.5Mb
• Access Time (max): 2.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 360mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

256K X 18 Pin Descriptions
Burst Address Table (MODE = NC/V
X18 BGA Pins
(external)
Address
A...A00
A...A01
A...A10
A...A11
First
4H
4G
3R
4K
4E
6B
2B
4F
4A
4B
(internal)
Address
Second
A...A01
A...A00
A...A11
A...A10
X18 QFP Pins
88
89
98
92
97
86
83
84
85
31
(internal)
Address
A...A10
A...A11
A...A00
A...A01
Third
MODE
ADSC
Name
ADSP
CLK
CE2
CE2
ADV
GW
CE
OE
CC
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
(internal)
Address
)
A...A11
A...A10
A...A01
A...A00
Fourth
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
input-
Static
Type
Input
6
Global Write: This active LOW input allows a full 18-bit Write
to occur independent of the BWE and WEn lines and must
meet the set-up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP .
Chip Enable: This active LOW input is used to enable the
device.
Chip enable: This active HIGH input is used to enable the
device.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
Address Status Controller: This active LOW input causes de-
vice to be de-selected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Burst Address Table (MODE = GND)
(external)
Address
A...A00
A...A01
A...A10
A...A11
First
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
(internal)
Address
Second
A...A01
A...A10
A...A11
A...A00
Description
(internal)
Address
A...A10
A...A11
A...A00
A...A01
Third
(internal)
Address
A...A11
A...A00
A...A01
A...A10
Fourth