CY7C1347C-200AC Cypress Semiconductor Corp, CY7C1347C-200AC Datasheet - Page 7

• Manufacturer Part Number: CY7C1347C-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347C-200AC

• Density: 4.5Mb
• Access Time (max): 2.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 360mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Truth Table
Partial Truth Table for READ/WRITE
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
Note:
2.
3.
4.
5.
6.
7.
8.
9.
X means “don’t care.” H means logic HIGH. L means logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.
For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
For X18 product, there are only BWa and BWb.
Operation
FUNCTION
[2, 3, 4, 5, 6, 7, 8]
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Used
None
None
None
None
None
Next
Next
Next
Next
Next
Next
GW
H
H
H
H
L
CE
[9]
H
X
H
H
H
H
H
X
H
L
L
L
L
L
L
L
L
L
X
X
X
X
CE2 CE2 ADSP
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
BWE
H
X
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
7
X
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
BWa
H
X
X
L
L
ADSC
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
L
L
L
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
ADV
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
BWb
H
H
X
X
L
WRITE
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
BWc
OE
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
H
H
L
L
L
L
L
L
X
X
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
BWd
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
H
H
X
L
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D