CY7C1355A-117AI Cypress Semiconductor Corp, CY7C1355A-117AI Datasheet - Page 21

• Manufacturer Part Number: CY7C1355A-117AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355A-117AI

• Density: 8Mb
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 410mA
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05265 Rev. *A
Switching Waveforms
BWa, BWb
BWc, BWd
Write Timing
Notes:
44. D(A
45. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when WEN signal is sampled LOW when ADV/LD
ADDRESS
ADV/LD
in the burst sequence of the base address A
state of the MODE input.
is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
ADV/LD
WEN
CLK
CEN
CKE
R/W
BW
DQx
CE
1
CLK
OE
OE
CE
A
) represents the first input to the external address A1. D(A
DQ
x
[40, 41, 42, 43, 44, 45]
BW(A
A
1
1
)
t
SD
Write
t
t
t
t
t
t
S
S
S
S
S
S
(continued)
BW(A
D(A
A
2
1
)
2
t
)
HD
Write
t
t
t
t
t
t
H
H
H
H
H
H
2
, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the
BW(A
D(A
2
+1)
2
)
t
KC
2
t
KL
BW(A
) represents the first input to the external address A
D(A
2
2
+2)
+1)
BW(A
D(A
2
2
+3)
+2)
Burst Write
t
KH
(CKE# HIGH, eliminates
current L-H clock edge)
BW(A
D(A
2
; D(A
2
(Burst Wraps around
+3)
2
)
to initial state)
2
+1) represents the next input data
CY7C1357A
CY7C1355A
D(A
2
)
Deselect
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