CY7C4251-10AI Cypress Semiconductor Corp, CY7C4251-10AI Datasheet
CY7C4251-10AI
Specifications of CY7C4251-10AI
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CY7C4251-10AI Summary of contents
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... High speed 100 MHz operation (10 ns read/write cycle time) ■ Low power ( mA) CC ■ Fully asynchronous and simultaneous read and write operation ■ ...
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Contents Features .............................................................................. 1 Functional Description ...................................................... 1 Logic Block Diagram ......................................................... 1 Contents ............................................................................. 2 Selection Guide ................................................................. 3 Pin Configuration .............................................................. 3 Functional Description ...................................................... 5 Architecture ....................................................................... 5 Resetting the FIFO ............................................................. 5 FIFO Operation .................................................................. 5 ...
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... The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. CY7C4421/4201/4211/4221 CY7C4231/4241/4251 -15 -25 Unit 66.7 40 MHz ICC1 40 40 CY7C4231 CY7C4241 CY7C4251 2K × × × 9 TQFP Top View WEN1 23 WCLK WEN2/ Description ...
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Table 1. Pin Definitions (continued) Pin Name I/O RCLK Read Clock EF Empty Flag O FF Full Flag O PAE Programmable O Almost Empty PAF Programmable O Almost Full RS Reset OE Output Enable Document #: 38-06016 Rev ...
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Functional Description The CY7C42X1 provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty – 7 and Full – 7. The flags are ...
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Figure 2. Offset Register Location and Default Values 64 × Empty Offset (LSB) Reg. Default Value = 007h Full Offset (LSB) Reg Default Value = 007h ...
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... The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK Empty Offset ( default value Full Offset ( default value). Document #: 38-06016 Rev. *D (512 – m), CY7C4221 CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. Table 2. Writing the Offset Registers LD WEN ...
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Width Expansion Configuration Word width may be increased by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and ...
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Maximum Ratings [4] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................... –65 Ambient Temperature with Power Applied .............................................. –55 Supply Voltage to Ground Potential................–0.5V to +7.0V DC Voltage Applied ...
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R1 1.1 K Ω 5V OUTPUT C L INCLUDING JIG AND Equivalent to: SCOPE Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH ...
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Switching Waveforms t CLKH WCLK D – WEN1 WEN2 (if applicable) FF [14] t SKEW1 RCLK REN1,REN2 t CLKH RCLK t t ENS ENH REN1,REN2 EF Q – OLZ OE WCLK WEN1 WEN2 Notes 14. ...
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RS REN1, REN2 WEN1 [17] WEN2/LD EF,PAE FF,PAF Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write WCLK – (FIRST 0 8 VALID t ENS WEN1 ...
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WCLK –D DATAWRITE1 ENH ENS WEN1 WEN2 (if applicable ENS ENH [19] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document ...
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NO Write WCLK [14] t SKEW1 D – WFF FF WEN1 WEN2 (if applicable) RCLK t ENH t ENS REN1, REN2 LOW –Q DATA IN OUTPUT REGISTER 0 8 Figure 11. Programmable Almost ...
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... PAF offset = m. 26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231, 4096 – m words for CY7C4241, 8192 – m words for CY7C4251. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of ...
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CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Document #: 38-06016 Rev. *D Figure 14. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4421/4201/4211/4221 CY7C4231/4241/4251 PAF OFFSET ...
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Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 25°C 0 100 MHz 0.6 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) NORMALIZED t vs. SUPPLY ...
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... CY7C4241-10AC CY7C4241-10AXC CY7C4241-10JI 15 CY7C4241-15AC CY7C4241-15JC CY7C4241-15JXC Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4251-10AC CY7C4251-10JC CY7C4251-10JXC CY7C4251-10AI CY7C4251-10AXI 15 CY7C4251-15AC CY7C4251-15AXC CY7C4251-15JC CY7C4251-15JXC Document #: 38-06016 Rev. *D Package Name Package Type J65 32-Pin Plastic Leaded Chip Carrier J65 32-Pin Pb-free Plastic Leaded Chip Carrier Package Name ...
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Package Diagrams Figure 15. 32-Pin Pb-free Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32, 51-85063 9.00±0.25 SQ 7.00±0. SEATING PLANE 1.20 MAX. 0.08 0.20 MAX. Figure 16. 32-Pin Pb-free Plastic Leaded Chip ...
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... ESH Added Pb-free logo to top of front page Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC, CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC, CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC, CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC, CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI, CY7C4251-15AXC, CY7C4251-15JXC Removed inactive/pruned parts from the Ordering Information table Added Table of Contents Updated TQFP package diagram cypress.com/go/plc ...