CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 118

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

14.0
Figure 14-1 shows how a Search engine subsystem can be formed using a host ASIC and an CYNSE70064A bank. It also shows
how this Search engine subsystem is integrated in a switch or router. The CYNSE70064A can access synchronous and
asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all search engines within a bank of search
engines.
15.0
The CYNSE70064A supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG standard
number 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and
TRST_L. Table 15-1 describes the operations that the test access port controller supports, and Table 15-2 describes the TAP
Device ID Register. Note. To disable JTAG functionality, connect the TCK, TMS and TDI pins to V
TRST_L to ground through a pull-down.
Table 15-1. Supported Operations
Document #: 38-02041 Rev. *F
SAMPLE/PRELOAD
Instruction
EXTEST
BYPASS
IDCODE
CLAMP
HighZ
Application
JTAG (1149.1) Testing
Figure 14-1. Sample Switch/Router Using the CYNSE70064A Device
Mandatory
Mandatory
Mandatory
Optional
Optional
Optional
Type
Sample/Preload. This operation loads the values of signals going to and from I/O
pins into the boundary scan shift register to provide a snapshot of the normal
functional operation, and to initialize boundary scan.
External Test. This operation uses boundary scan values shifted in from TAP to
test connectivity external to the device.
This operation loads a single bit shift register between TDI and TDO and provides
a minimum-length serial path when no test operation is required
This operation selects the Identification register between TDI and TDO and allows
the “idcode” to be read serially through TDO.
This operation drives preset values onto the outputs of devices
This operation leaves the device output pins in a high-impedance state.
Description
DDQ
CYNSE70064A
through a pull-up, and
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