CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 94

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

10.16
When search engines are cascaded using multiple CYNSE70064As, the SADR, CE_L, and WE_L (three-state signals) are all
tied together. In order to eliminate external pull-ups and pull-downs, one device in a bank is designated as the default driver. For
non-Search or non-Learn cycles (see Subsection 10.17, “Learn Command” on page 94) or Search cycles with a global miss, the
SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of
search engines that are cascaded have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L and can
potentially cause damage to the device(s).
Similarly, when search engines using multiple CYNSE70064As are cascaded, SSF and SSV (also three-state signals) are tied
together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For
nonSearch cycles or Search cycles with a global miss the SSF and SSV signals are driven by the device with the LDEV bit set.
It is important that only one device in a bank of search engines that are cascaded together have this bit set. Failure to do so will
cause contention on SSV and SSF and can potentially cause damage to the device(s).
10.17
Bit[0] of each 68-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied,
the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between
depth-cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines
the fullness of the depth-cascaded table.
The device contains 16 pairs of internal, 68-bit-wide comparand registers that store the comparands as the device executes
searches. On a miss by the Search signalled to ASIC through the SSV and SSF signals (SSV = 1, SSF = 0), the host ASIC can
apply the Learn command to learn the entry from a comparand register to the next-free location (see Subsection 7.8, “NFA
Register” on page 17). The NFA updates to the next-free location following each Write or Learn command.
In a depth-cascaded table, only a single device will learn the entry through the application of a Learn instruction. The determination
of which device is going to learn is based on the FULI and FULO signalling between the devices. The first non-full device learns
the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA.
In a ×68-configured table the Learn command writes a single 68-bit location. In a ×136-configured table the Learn command
writes the next even and odd 68-bit locations. In 136-bit mode, bit[0] of the even and odd 68-bit locations is 0, which indicates
that they are cascaded empty, or 1, which indicates that they are occupied.
The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no
more entries can be learned. The CYNSE70064A updates the signal after each Write or Learn command to a data array. The
Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see
Section 12.0, “SRAM Addressing” on page 101).
The Learn command is supported on a single block containing up to eight devices if the table is configured either as a ×68 or
a ×136. The Learn command is not supported for ×272-configured tables.
Learn is a pipelined operation and lasts for two CLK cycles, as shown in Figure 10-73 where TLSZ = 00, and Figure 10-74 and
Figure 10-75 where TLSZ = 01. Figure 10-74 and Figure 10-75 assume that the device performing the Learn operation is not the
last device in the table and has its LRAM bit set to 0. Note. The OE_L for the device with the LRAM bit set goes HIGH for two
cycles for each Learn (one during the SRAM Write cycle, and one the cycle before). The latency of the SRAM Write cycle from
the second cycle of the instruction is shown in Table 10-34.
Document #: 38-02041 Rev. *F
LRAM and LDEV Description
Learn Command
CYNSE70064A
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