APA075-TQ100I MICROSEMI, APA075-TQ100I Datasheet - Page 173

• Manufacturer Part Number: APA075-TQ100I
• Manufacturer: MICROSEMI

Specifications of APA075-TQ100I

• Family Name: ProASICPLUS®
• Number Of Usable Gates: 75000
• # Registers: 3072
• # I/os (max): 66
• Frequency (max): 180MHz
• Process Technology: 0.22um (CMOS)
• Operating Supply Voltage (typ): 2.5V
• Ram Bits: 27648
• Device System Gates: 75000
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 2.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Previous version
v2.0
(continued)
The following pins have been changed in the
Pin Number
10
11
13
15
16
"144-Pin TQFP" section
The following pins have been changed in the
Pin Number
23
24
26
28
30
The following pins have been changed in the
Pin Number
M1
M2
M22
N2
N4
The following pins have been changed in the
Pin Number
C2
D12
E11
F1
F3
The following pins have been changed in the
Pin Number
H1
H2
H3
H13
H14
The following pins have been changed in the
Pin Number
L4
L5
L6
L16
L17
The following pins have been changed in the
Pin Number
N1
N3
N5
N22
N24
The following pins have been changed in the
Pin Number
R2
R4
R5
R27
R29
Changes in current version (v5.9)
Function
I/O (GLMX1)
GL1
NPECL1
PPECL1(I/P)
GL2
Function
I/O (GLMX1)
GL1
NPECL1
PPECL1 (I/P)
GL2
Function
GL1
GL2
GL4
I/O (GLMX1)
PPECL1 (I/P)
Function
GL2
I/O (GLMX2
NPECL2
GL1
I/O (GLMX1)
Function
GL1
NPECL1
I/O (GLMX1)
I/O (GLMX2)
NPECL2
Function
GL1
NPECL1
I/O (GLMX1)
I/O (GLMX2)
NPECL2
Function
GL1
I/O (GLMX1)
NPECL1
GL3
NPECL2
Function
I/O (GLMX1)
NPECL1
GL1
NPECL2
I/O (GLMX2)
is new.
v5.9
"100-Pin TQFP"
"208-Pin PQFP"
"456-Pin PBGA"
"144-Pin FBGA"
"256-Pin FBGA"
"484-Pin FBGA"
"676-Pin FBGA"
"896-Pin FBGA"
Pin Number
60
61
63
65
66
Pin Number
128
129
132
134
135
Pin Number
N22
N23
N25
P5
P26
Pin Number
F9
)F11
F12
G1
G4
Pin Number
H16
J1
J2
J13
J16
Pin Number
L19
M4
M5
M16
M19
Pin Number
N25
P1
P5
P22
P24
Pin Number
T3
T4
T26
T27
T28
table:
table:
table:
table:
table:
table:
table:
table:
Function
GL3
PPECL2 (I/P)
NPECL2
GL4
I/O (GLMX2)
Function
GL3
PPECL2 (I/P)
NPECL2
GL4
I/O (GLMX2)
Function
NPECL2
GL3
I/O (GLMX2)
NPECL1
PPECL2 (I/P)
Function
GL4
PPECL2 (I/P
GL3
PPECL1 (I/P)
NPECL1
Function
GL4
GL2
PPECL1 (I/P)
PPECL2 (I/P)
GL3
Function
GL4
GL2
PPECL1 (I/P)
PPECL2 (I/P)
GL3
Function
GL4
GL2
PPECL1 (I/P)
I/O (GLMX2)
PPECL2 (I/P)
Function
GL2
PPECL1 (I/P)
PPECL2 (I/P)
GL4
GL3
ProASIC
PLUS
Flash Family FPGAs
Page
3-22
3-37
3-40
3-45
3-51
3-59
3-1
3-3
3-5
4-5